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Patent # Description
2017/0256320 Adaptive Determination Of Program Parameter Using Program Of Erase Rate
Techniques are provided for optimizing the programming of memory cells by obtaining a metric which indicates a program or erase rate of the memory cells. In...
2017/0256319 APPARATUSES AND METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS
The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory...
2017/0256318 SEMICONDUCTOR MEMORY DEVICE WITH MEMORY CELLS EACH INCLUDING A CHARGE ACCUMULATION LAYER AND A CONTROL GATE
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control...
2017/0256317 Techniques For Programming Of Select Gates In NAND Memory
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some...
2017/0256316 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a...
2017/0256315 RESISTIVE MEMORY TRANSITION MONITORING
A circuit for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The circuit includes a...
2017/0256314 RESISTIVE RANDOM ACCESS MEMORY AND WRITE OPERATION METHOD THEREOF
The present invention relates to resistive random access memory (ReRAM). Disclosed are a ReRAM and write operation method thereof. The write operation method...
2017/0256313 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled...
2017/0256312 MEMORY DEVICE
A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a...
2017/0256311 METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCREASING PIN COST
A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address...
2017/0256310 RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR OPERATING SAME
A resistance random access memory device includes a control circuit. The control circuit applies a first voltage between the plurality of second interconnects...
2017/0256309 NONVOLATILE MEMORY DEVICE INCLUDING PAGE BUFFER AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE
A nonvolatile memory device including a page buffer and a method of operating the nonvolatile memory device, the method including performing a first sensing...
2017/0256308 NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical...
2017/0256307 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE
To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a...
2017/0256306 Memory Array with Bit-Lines Connected to Different Sub-Arrays Through Jumper Structures
An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells,...
2017/0256305 WEAR LEVELING FOR STORAGE OR MEMORY DEVICE
A method of wear leveling for a storage device or a memory device includes: receiving an inputted memory address; randomizing the inputted memory address to be...
2017/0256304 TECHNOLOGIES FOR SECURE CONTENT DISPLAY WITH PANEL SELF-REFRESH
Technologies for secure content display include a computing device having a display controller and a display. The display includes a self-refresh frame buffer....
2017/0256303 ASYMMETRIC ON-STATE RESISTANCE DRIVER OPTIMIZED FOR MULTI-DROP DDR4
An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a...
2017/0256302 Dynamic Random Access Memory For Communications Systems
An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, and DRAM cells. A first portion of the DRAM cells may be refreshed by the...
2017/0256301 MEMORY DEVICE AND SEMICONDUCTOR DEVICE
To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a...
2017/0256300 GROUND REFERENCE SCHEME FOR A MEMORY CELL
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line...
2017/0256299 TIME TRACKING CIRCUIT FOR FRAM
Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a...
2017/0256298 MAGNETIC STORAGE DEVICE
According to one embodiment, a magnetic storage device includes memory cells, wherein each of the memory cell includes: a wiring including a first...
2017/0256297 READ LATENCY REDUCTION IN A MEMORY DEVICE
A memory device can include: a memory array with memory cells arranged as data lines; an interface that receives a read command requesting bytes of data in a...
2017/0256296 DIGITAL PERCEPTRON
In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for...
2017/0256295 SYNCHRONIZATION AFTER A MEMORY MODE SWITCH
An apparatus includes a transmitter and a controller. The transmitter may be configured to transmit data stored in a memory. The controller may be configured...
2017/0256294 SEMICONDUCTOR DEVICE
A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive...
2017/0256293 SENSING BUFFER, PERIPHERAL CIRCUIT, AND/OR MEMORY DEVICE
A sensing buffer, or peripheral circuit or memory device may be provided. The sensing buffer may be configured to maintain a predetermined current according to...
2017/0256292 MEMORY ARRAY POWER REDUCTION THROUGH REDUCED SUPPLY VOLTAGE
Systems, apparatuses, and methods for implementing a storage array with a voltage regulator circuit. An integrated circuit (IC) may include a storage array,...
2017/0256291 MEMORY MODULE WITH PACKAGES OF STACKED MEMORY CHIPS
A memory module is operable in a computer system to communicate with a system memory controller via a command/address bus and a data bus. The memory module...
2017/0256290 STACKED DRAM DEVICE AND METHOD OF MANUFACTURE
A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output...
2017/0256289 SYSTEMS AND METHODS FOR AUTOMATING IDENTIFICATION AND DISPLAY OF VIDEO DATA SETS
A system for identifying, tagging, and displaying one or more assets within an audio visual (AV) file includes an asset tagging server, an asset tag...
2017/0256288 METHODS AND SYSTEMS OF VIDEO PROCESSING
Methods and systems are provided for video processing. Video may be captured using an image capture device at a first definition. The image capture device may...
2017/0256287 MOBILE DEVICE VIDEO PERSONALIZATION
The disclosure includes embodiments for generating a synched video. A method includes determining a duration and a number of discrete frames of an original...
2017/0256286 Audio Capture on Mobile Client Devices
Audio capture techniques on mobile client devices are described. In one or more implementations, techniques are described for leveraging availability of audio...
2017/0256285 VIDEO PROCESSING METHOD AND VIDEO PROCESSING SYSTEM
A video processing method and a video processing system for processing an original video are provided. The original video includes a plurality of original...
2017/0256284 VIDEO EDITING APPARATUS, VIDEO EDITING METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
A video editing apparatus includes a storing unit, an input unit, a segment selection unit, and a generation unit. The storing unit stores video data along...
2017/0256283 INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD
Excellent information processing device, information processing method, and information processing system capable of viewing a content without temporal and...
2017/0256282 MAGNETIC TAPE APPLIANCE WITH SELECTABLY ALWAYS-LEADING HEAD ASSEMBLIES
A tape appliance includes first and second tape head modules, and a guide surface with first and second slots. The guide surface is configured such that the as...
2017/0256281 SYSTEMS AND METHODS FOR REDUCING AUDIO DISTORTION DURING PLAYBACK OF PHONOGRAPH RECORDS USING MULTIPLE TONEARM...
Systems and methods are disclosed relating to electro-mechanical devices and related computer control and audio processing systems intended to optimize...
2017/0256280 OPTICAL DISC APPARATUS CONTROLLING IRRADIATION POSITION BASED ON CROSS-CORRELATION VALUE BETWEEN REPRODUCTION...
In an optical disc apparatus for reproducing information recorded on a track of an optical disc, an optical head irradiates a light beam onto the track,...
2017/0256279 QUADRATURE TRACK ERROR SIGNAL FOR OPTICAL RECORDING MEDIA AND DEVICES
A method for providing tracking error signals in an optical data storage system includes a step of receiving a wobble signal having a first frequency from the...
2017/0256278 MAGNETIC-DISK SUBSTRATE HAVING A SMALL WAVINESS, FOR USE AS A MAGNETIC DISK, AND A MAGNETIC-DISK DRIVE DEVICE...
When waviness having a wavelength component of 10 to 500 .mu.m in the circumferential direction of a main surface of a disk-shaped substrate is acquired and...
2017/0256277 OFFSET WAVEGUIDE SYSTEM WITH A MODE CONVERTER AND A TAPERED BEND
A read/write head has an input coupler that receives light at a fundamental mode from an energy source. A mode converter of the read/write head converts light...
2017/0256276 MULTI READER HEAD HAVING A VARYING GAP LAYER LAMINATED BETWEEN READERS
A multi reader head has a plurality of readers that are laminated via a gap layer(s), and each of the readers has a structure in which a ...
2017/0256275 HEATER DESIGN FOR FLY HEIGHT CONTROL
Implementations described and claimed herein includes a storage device comprising a transducer heat including at least one pair of read/write elements and a...
2017/0256274 THIN FILM MAGNETIC HEAD, HEAD GIMBALS ASSEMBLY, HEAD ARM ASSEMBLY, AND MAGNETIC DISK UNIT
This thin film magnetic head includes: a magnetic pole including a first end surface exposed on an air bearing surface; a coil configured to provide a magnetic...
2017/0256273 MAGNETIC RECORDING AND REPRODUCING DEVICE
According to one embodiment, a magnetic recording and reproducing device includes a magnetic recording medium, a magnetic head, and a controller. The...
2017/0256272 METHOD AND APPARATUS FOR FAST RECOGNITION OF A HEARING DEVICE USER'S OWN VOICE, AND HEARING AID
A method for fast recognition of a hearing aid wearer's own voice, and a corresponding apparatus for carrying out the method. The hearing aid receives audio...
2017/0256270 Voice Recognition Accuracy in High Noise Conditions
Systems and methods for voice recognition determine energy levels for speech and noise and generate adaptive thresholds based on the determined energy levels....
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