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Patent # Description
2017/0287867 ANISOTROPIC CONDUCTIVE FILM INCLUDING A REFLECTIVE LAYER
An anisotropic conductive film (ACF) is disclosed. In one approach, the ACF includes a non-reflective adhesive layer including a top surface, a plurality of...
2017/0287866 INTERLAYER FILLER COMPOSITION FOR SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
To provide an interlayer filler composition capable of forming a cured adhesive layer sufficiently cured and excellent in adhesion without letting voids be...
2017/0287865 PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a...
2017/0287864 BOND PAD WITH MICRO-PROTRUSIONS FOR DIRECT METALLIC BONDING
A bond pad with micro-protrusions for direct metallic bonding. In one embodiment, a semiconductor device comprises a semiconductor substrate, a through-silicon...
2017/0287863 SEMICONDUCTOR DIE, SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME
A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has...
2017/0287862 Cu Column, Cu Core Column, Solder Joint, and Through-Silicon Via
Provided are a Cu column, a Cu core column, a solder joint, and a through-silicon via, which have the low Vickers hardness and the small arithmetic mean...
2017/0287861 Cu PILLAR CYLINDRICAL PREFORM FOR SEMICONDUCTOR CONNECTION
A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form...
2017/0287860 SURFACE FINISHES FOR HIGH DENSITY INTERCONNECT ARCHITECTURES
An electroless nickel, electroless palladium, electroless tin stack and associated methods are shown. An example method to form a solder bump may include...
2017/0287859 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in...
2017/0287858 SEMICONDUCTOR DEVICE WITH MODIFIED PAD SPACING STRUCTURE
A semiconductor device is provided, including a substrate, an interconnection structure formed on the substrate, a first top conductive layer formed on the...
2017/0287857 UNDER-BUMP METAL STRUCTURES FOR INTERCONNECTING SEMICONDUCTOR DIES OR PACKAGES AND ASSOCIATED SYSTEMS AND METHODS
The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package...
2017/0287856 ELECTRONIC COMPONENT PACKAGE
An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the...
2017/0287855 VARIABLE HANDLE WAFER RESISTIVITY FOR SILICON-ON-INSULATOR DEVICES
Variable handle wafer resistivity for silicon-on-insulator devices. In some embodiments, a radio-frequency device can include a silicon-on-insulator substrate...
2017/0287854 TUNABLE ACTIVE SILICON FOR COUPLER LINEARITY IMPROVEMENT AND RECONFIGURATION
An electromagnetic coupler assembly includes a handle wafer having an oxide layer disposed on a first surface thereof. A layer of active semiconductor is...
2017/0287853 FAN-OUT SEMICONDUCTOR PACKAGE
The fan-out semiconductor package includes: a semiconductor chip having an active surface having a connection pad disposed thereon and an inactive surface...
2017/0287852 SEMICONDUCTOR PACKAGE
A semiconductor package includes: a first substrate including a first ground conductor disposed on at least a second surface of a first surface and the second...
2017/0287851 SEMICONDUCTOR PACKAGE HAVING AN EMI SHIELDING LAYER
Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer...
2017/0287850 Stacked Die Ground Shield
The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices...
2017/0287849 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: providing, on a substrate, a first magnetic substrate including a base, a first side wall portion...
2017/0287848 ELECTRONIC CIRCUIT PACKAGE USING COMPOSITE MAGNETIC SEALING MATERIAL
Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold...
2017/0287847 INTEGRATED CIRCUIT PACKAGE HAVING INTEGRATED EMI SHIELD
Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can...
2017/0287846 SYSTEMS AND METHODS FOR ELECTROMAGNETIC INTERFERENCE SHIELDING
Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate...
2017/0287845 Alignment Mark Design for Packages
A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment...
2017/0287844 3D INTEGRATED CIRCUIT DEVICE
A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second...
2017/0287843 SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS WITH DIFFERENT INTERFACIAL LAYERS
According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a...
2017/0287842 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the...
2017/0287841 THROUGH VIA STRUCTURE FOR STEP COVERAGE IMPROVEMENT
A semiconductor device includes a substrate, a dielectric structure, a barrier layer, a glue layer, a copper seed layer and a copper layer. The dielectric...
2017/0287840 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having...
2017/0287839 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME
A fan-out semiconductor package includes a redistribution layer, the redistribution layer including a first insulating layer, a first wiring disposed on the...
2017/0287838 ELECTRICAL INTERCONNECT BRIDGE
Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material....
2017/0287837 DUAL METAL-INSULATOR-SEMICONDUCTOR CONTACT STRUCTURE AND FORMULATION METHOD
A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain...
2017/0287836 NON-SYMMETRIC BODY CONTACTS FOR FIELD-EFFECT TRANSISTORS
Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to...
2017/0287835 Combined Source And Base Contact For A Field Effect Transistor
The present disclosure relates to semiconductor devices. The teachings thereof may be embodied in metal oxide semiconductor field effect transistors (MOSFET)...
2017/0287834 Contact Expose Etch Stop
The present disclosure relates to semiconductor devices and the teachings thereof may be embodied in metal oxide semiconductor field effect transistors...
2017/0287833 THREE DIMENSIONAL STORAGE CELL ARRAY WITH HIGHLY DENSE AND SCALABLE WORD LINE DESIGN APPROACH
An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having...
2017/0287832 SEMICONDUCTOR PACKAGE DEVICES INTEGRATED WITH INDUCTOR
The present disclosure provides an inductor structure. The inductor structure, comprising a first surface, a second surface intersecting with the first...
2017/0287831 LOCALIZED HIGH DENSITY SUBSTRATE ROUTING
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus...
2017/0287830 TREATING COPPER INTERCONNECTS
Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the...
2017/0287829 METHOD AND IC STRUCTURE FOR INCREASING PITCH BETWEEN GATES
Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present...
2017/0287828 SEMICONDUCTOR MODULE
A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad...
2017/0287827 SEMICONDUCTOR PACKAGE SUBSTRATE HAVING AN INTERFACIAL LAYER
Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate...
2017/0287826 MONOLITHIC 3D INTEGRATION INTER-TIER VIAS INSERTION SCHEME AND ASSOCIATED LAYOUT STRUCTURE
A 3D-IC includes a first tier device and a second tier deice. The first tier device and the second tier device are vertically stacked together. The first tier...
2017/0287825 FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME
A fan-out semiconductor package include a frame having a through hole; a semiconductor chip disposed in the through hole, and having an active surface, an...
2017/0287824 DEVICE WITH PILLAR-SHAPED COMPONENTS
A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the...
2017/0287823 MOUNTING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a mounting substrate according to an embodiment of the present technology includes the following three steps: (1) a step of forming a...
2017/0287822 ELECTRONIC APPARATUS WITH POCKET OF LOW PERMITTIVITY MATERIAL TO REDUCE ELECTROMAGNETIC INTERFERENCE
An electronics apparatus including a first substrate having a first surface and a second surface, a first switch connected to a second switch and soldered in...
2017/0287821 POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located...
2017/0287820 Semiconductor Package Having a Source-Down Configured Transistor Die and a Drain-Down Configured Transistor Die
A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first...
2017/0287818 SEMICONDUCTOR DEVICE AND AN ELECTRONIC DEVICE
A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of...
2017/0287817 SEMICONDUCTOR DEVICE
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is...
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