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Patent # Description
2017/0287816 LEADFRAME TOP-HAT MULTI-CHIP SOLUTION
A semiconductor package may include an electrically conductive leadframe having a aperture extending from an upper surface of the leadframe to the lower...
2017/0287815 PACKAGE SUBSTRATE, PACKAGE STRUCTURE INCLUDING THE SAME, AND THEIR FABRICATION METHODS
This disclosure provides a package substrate, a package structure including the same and their fabrication methods. The package substrate comprises: a first...
2017/0287814 CHIP-ON-FILM SEMICONDUCTOR PACKAGES AND DISPLAY APPARATUS INCLUDING THE SAME
Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF...
2017/0287813 BODY CONTACTS FOR FIELD-EFFECT TRANSISTORS
Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to...
2017/0287812 TRANSISTOR STRUCTURES GATED USING A CONDUCTOR-FILLED VIA OR TRENCH
Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A...
2017/0287811 SEMICONDUCTOR DEVICE
A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided...
2017/0287810 HEAT RADIATING MEMBER AND METHOD FOR PRODUCING THE SAME
A heat radiating member includes: a composite portion composed of a composite material which contains particles of a satisfactorily thermally conductive...
2017/0287809 COMPLIANT PIN FIN HEAT SINK WITH BASE INTEGRAL PINS
A compliant pin fin heat sink includes a flexible base plate having a thickness of from about 0.2 mm to about 0.5 mm. A plurality of pins extends from the...
2017/0287808 DUAL-SIDED DIE PACKAGES
An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of...
2017/0287807 ELECTRONICS PACKAGE WITH IMPROVED THERMAL PERFORMANCE
An electronics package includes a thermal lid over a flip chip component such that the thermal lid is in contact with a surface of a flip chip component and...
2017/0287806 ELECTRONIC DEVICE PROVIDED WITH A THERMAL DISSIPATION MEMBER
An electronic device includes a support and a component in the form of an integrated circuit chip having a rear face mounted above a front face of the support...
2017/0287805 SEMICONDUCTOR DEVICE
A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate bonded to an upper...
2017/0287804 Apparatus and Method to Support Thermal Management of Semiconductor-Based Components
An integrated circuit having a body comprised of semiconducting material has one or more electronic components formed in a first region of the body and at...
2017/0287803 EXTENDED TEMPERATURE OPERATION FOR ELECTRONIC SYSTEMS USING INDUCTION HEATING
Embodiments are generally directed to extended temperature operation for electronic systems using induction heating. An embodiment of an apparatus includes an...
2017/0287802 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR APPARATUS
A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate...
2017/0287801 MULTI-CHIP PACKAGE STRUCTURE MANUFACTURING PROCESS AND WAFER LEVEL CHIP PACKAGE STRUCTURE MANUFACTURING PROCESS
A wafer level chip package manufacturing process is provided. A wafer includes a plurality of first chips and a circuit layer disposed on the first chips,...
2017/0287800 SEALING SHEET
Provided is a sealing sheet capable of preventing void and filler segregation from occurring when forming a sealing body in which semiconductor chips are...
2017/0287799 REMOVABLE IC PACKAGE STIFFENER
A stiffener, an IC package and methods of fabrication of an IC package including a removable stiffener are shown. A removable stiffener for use with an...
2017/0287798 Baseplate for an electronic module and method of manufacturing the same
Various embodiments provide an electronic module comprising a baseplate. A recess is formed in one main surface of the baseplate, wherein the recess is adapted...
2017/0287797 CHIP PACKAGING METHOD AND PACKAGE STRUCTURE
A chip packaging method and package structure, the package structure including a substrate, a sensing chip coupled to the substrate, a plastic package layer...
2017/0287796 ELECTRONIC COMPONENT PACKAGE
An electronic component package includes: a lower package, including a frame including a through-hole and a through-wiring, a first electronic component...
2017/0287795 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
When VC inspection for a TEG is performed, it is easily detected whether any failure of a contact plug occurs or not by increasing an emission intensity of a...
2017/0287794 METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND FOR DETECTING END POINT OF DRY ETCHING
A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the...
2017/0287793 APPARATUS AND METHOD TO CONTROL ETCH RATE THROUGH ADAPTIVE SPIKING OF CHEMISTRY
An apparatus and method are provided to: determine a unique profile to etch each wafer, execute that etch, and determine and deliver the proper chemical...
2017/0287792 GENERAL FOUR-PORT ON-WAFER HIGH FREQUENCY DE-EMBEDDING METHOD
The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy,...
2017/0287791 CONTROLLING DRY ETCH PROCESS CHARACTERISTICS USING WAFERLESS DRY CLEAN OPTICAL EMISSION SPECTROSCOPY
Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry...
2017/0287790 Defectivity Metrology During DSA Patterning
The described embodiments include performing a curing process for selective treatment, or hardening, of PS regions in PS-b-PMMA block copolymer DSA films prior...
2017/0287789 PRESSURE-ACTIVATED ELECTRICAL INTERCONNECTION BY MICRO-TRANSFER PRINTING
A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one...
2017/0287788 EXTRA GATE DEVICE FOR NANOSHEET
A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is...
2017/0287787 METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE...
A method of manufacturing a semiconductor device includes configuring a layout pattern; and forming conductive lines corresponding to the layout pattern on a...
2017/0287786 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A process of forming a first mask on a first region of a metal film formed on a surface of a substrate, a process of modulating a work function of a first...
2017/0287785 HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
2017/0287784 VERTICAL AIR GAP SUBTRACTIVE ETCH BACK END METAL
After forming source/drain contact structures within an interlevel dielectric (ILD) layer to contact source/drain regions of a field effect transistor (FET),...
2017/0287783 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method which improves working efficiency. The method includes the step of transporting by air a package as a sealed...
2017/0287782 IR ASSISTED FAN-OUT WAFER LEVEL PACKAGING USING SILICON HANDLER
A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface...
2017/0287781 SHELL STRUCTURE FOR INSULATION OF A THROUGH-SUBSTRATE INTERCONNECT
Techniques and mechanisms for providing electrical insulation of a through-substrate interconnect (TI). In an embodiment, the TI extends between a first side...
2017/0287780 METHODS OF FORMING SELF-ALIGNED CONTACT STRUCTURES BY WORK FUNCTION MATERIAL LAYER RECESSING AND THE RESULTING...
One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is...
2017/0287779 Method of Forming Contact Metal
A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain...
2017/0287778 METHOD AND APPARATUS FOR FORMING SILICON FILM AND STORAGE MEDIUM
A silicon film forming method of forming a silicon film in a recess with respect to a target substrate having on its surface an insulating film in which the...
2017/0287777 METHODS OF FORMING MIS CONTACT STRUCTURES ON TRANSISTOR DEVICES
One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a...
2017/0287776 HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
2017/0287775 Interconnect Structure Having an Etch Stop Layer Over Conductive Lines
A multilayer interconnect structure for integrated circuits includes a first dielectric layer over a substrate and a conductive line partially exposed over the...
2017/0287774 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A first silicon oxide film is formed on the inner wall of a deep trench by oxidizing the inner wall of the deep trench while heating the inner wall. Then, a...
2017/0287773 Systems and Methods for a Semicdonductor Structure Having Multiple Semiconductor-Device Layers
A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor...
2017/0287772 Silicon on Nothing Devices and Methods of Formation Thereof
In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The...
2017/0287771 STRETCHING RETENTION PLATE FOR ELECTRONIC ASSEMBLIES
A substrate retention plate system for holding a substrate for processing in an electronic device manufacturing process is described. The retention plate...
2017/0287770 Apparatus And Methods For Wafer Rotation In Carousel Susceptor
Apparatus and method for processing a plurality of substrates in a batch processing chamber are described. The apparatus comprises a susceptor assembly, a lift...
2017/0287769 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD
A substrate processing apparatus includes a substrate holding unit which holds and rotates a substrate in a horizontal orientation, a substrate heating unit...
2017/0287768 Apparatus and Method to Improve Plasma Dicing and Backmetal Cleaving Process
An apparatus and method to improve the plasma dicing and backmetal cleaving process on substrates through the use of pressurized deionized water (DI) dispense...
2017/0287767 SUBSTRATE TRANSFER APPARATUS, SUBSTRATE PROCESSING APPARATUS, AND SUBSTRATE PROCESSING METHOD
According to one embodiment, a substrate transfer apparatus includes: a first gripping plate; a first claw that is supported by the first gripping plate, and...
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