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Patent # Description
2017/0286344 Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a Chip
An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected...
2017/0286343 TRANSMITTING UNIVERSAL SERIAL BUS (USB) DATA OVER ALTERNATE MODE CONNECTION
An example includes an apparatus for transmitting Universal Serial Bus (USB) packets. The apparatus includes a transmitter adapter to receive a USB packet from...
2017/0286342 Determination of Timing Configurations for Program Dataflow Models
A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow...
2017/0286341 COMMUNICATION SYSTEM, COMMUNICATION SYSTEM CONTROL METHOD, AND PROGRAM
Communication systems and communication control methods are disclosed. In one example, a slave device belonging to a group of devices to which arbitration is...
2017/0286340 SLAVE DEVICE IDENTIFICATION ON A SINGLE WIRE COMMUNICATIONS BUS
A system includes a single wire communications bus, a first slave device, and a second slave device. The first slave device and the second slave device each...
2017/0286339 Modular Chassis with Fabric Integrated into the Line Card
In one embodiment, a system includes a number of application-specific integrated circuits (ASICs). At least one of the ASICs is configured to process incoming...
2017/0286338 METHODS AND APPARATUS FOR COMBINING MULTIPLE, CODEPENDENT, MEDIA AGNOSTIC USB OPERATIONS
Methods and apparatus to combine multiple codependent media agnostic USB operations are disclosed. An example method includes receiving a transmission from a...
2017/0286337 TECHNOLOGIES FOR A DISTRIBUTED HARDWARE QUEUE MANAGER
Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as...
2017/0286336 DIRECT DRIVE LED DRIVER AND OFFLINE CHARGE PUMP AND METHOD THEREFOR
In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn...
2017/0286335 Interconnect Distributed Virtual Memory Message Preemptive Responding
Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM...
2017/0286334 ENHANCED DIRECTED SYSTEM MANAGEMENT INTERRUPT MECHANISM
A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle...
2017/0286333 Arbiter Based Serialization of Processor System Management Interrupt Events
A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of...
2017/0286332 TECHNOLOGIES FOR PROCESSOR CORE SOFT-OFFLINING
Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system...
2017/0286330 READ TRAINING A MEMORY CONTROLLER
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits...
2017/0286329 MUTUAL EXCLUSION IN A NON-COHERENT MEMORY HIERARCHY
Methods and systems for mutual exclusion in a non-coherent memory hierarchy may include a non-coherent memory system with a shared system memory. Multiple...
2017/0286328 DATA TRANSFER BETWEEN HOST AND PERIPHERAL DEVICES
A device, which may be a peripheral device or a host computing device, comprises a communication interface, a memory and a processor. The processor is arranged...
2017/0286327 Multi-Standard Single Interface With Reduced I/O Count
An apparatus is described having an electrical interface that supports a first specification and a second specification. The first specification specifies...
2017/0286326 MEMORY PROTECTION AT A THREAD LEVEL FOR A MEMORY PROTECTION KEY ARCHITECTURE
A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management...
2017/0286325 METHOD AND SYSTEM FOR DEFINING LOGICAL BLOCK ADDRESSING (LBA) ACCESS PERMISSION IN STORAGE DEVICES
Method, system, apparatus, and/or non-transitory computer readable medium for customizing data access permission in a data storage system. The system allows...
2017/0286324 SEMICONDUCTOR DEVICE AND ACCESS MANAGEMENT METHOD
A semiconductor device includes a plurality of processing units, a shared resource shared by the plurality of processing units, and a guard unit. The guard...
2017/0286323 MEMORY ACCESS PROTECTION APPARATUS AND METHODS
Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with...
2017/0286322 MEMORY ACCESS PROTECTION APPARATUS AND METHODS
Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window...
2017/0286321 DUAL-SYSTEM-BASED DATA STORAGE METHOD AND TERMINAL
A dual-system-based data storage method, comprising the steps of (S301) judging whether the data is important data when storing data in a first system; and...
2017/0286320 AVOIDING REDUNDANT MEMORY ENCRYPTION IN A CRYPTOGRAPHIC PROTECTION SYSTEM
This disclosure is directed to avoiding redundant memory encryption in a cryptographic protection system. Data stored in a device may be protected using...
2017/0286319 Securing Information Relating to Data Compression and Encryption in a Storage Device
Apparatus and method for data security in a data storage environment. In some embodiments, input data from a host is received into a buffer memory. Data...
2017/0286318 TECHNIQUES TO PROVIDE A SECURE SYSTEM MANAGEMENT MODE
Various embodiments are generally directed to an apparatus, method and other techniques for allocating a portion of the memory as system management random...
2017/0286317 ALTERNATIVE DIRECT-MAPPED CACHE AND CACHE REPLACEMENT METHOD
A method includes storing a first block of main memory in a cache line of a direct-mapped cache, storing a first tag in a current tag field of the cache line,...
2017/0286316 APPARATUS AND METHOD FOR LAZY TRANSLATION LOOKASIDE BUFFER (TLB) COHERENCE
An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute...
2017/0286315 MANAGING TRANSLATION INVALIDATION
Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs)...
2017/0286314 HARDWARE-BASED TRANSLATION LOOKASIDE BUFFER (TLB) INVALIDATION
Hardware-based translation lookaside buffer (TLB) invalidation techniques are disclosed. A host system is configured to exchange data with a peripheral...
2017/0286313 METHOD AND APPARATUS FOR ENABLING LARGER MEMORY CAPACITY THAN PHYSICAL MEMORY SIZE
A method of retrieving data stored in a memory associated with a dedupe module is provided. The method includes: identifying a logical address of the data;...
2017/0286312 DELEGATED MEDIA TRANSLATION LAYER IN A STORAGE APPLIANCE
In general, embodiments of the technology relate to writing data to and reading data from storage appliances. More specifically, embodiments of the technology...
2017/0286311 REPETITIVE ADDRESS INDIRECTION IN A MEMORY
In one embodiment, repetitive address indirection is employed to repetitively redirect write operations to different physical locations of the memory. In one...
2017/0286310 TECHNOLOGIES FOR REGION-BIASED CACHE MANAGEMENT
Technologies for region-based cache management includes network computing device. The network computing device is configured to divide an allocated portion...
2017/0286309 WRITE CACHE SYSTEM AND METHOD
A method, computer program product, and computer system for receiving, at a first computing device, a first data chunk sent from a second computing device. It...
2017/0286308 PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT...
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some...
2017/0286307 Optimized Read Cache For Persistent Cache On Solid State Devices
Systems and methods for a content addressable cache that is optimized for SSD use are disclosed. In some embodiments, the cache utilizes an identifier array...
2017/0286306 DATA ACCESSING METHOD AND APPARATUS
A data accessing method includes: determining whether a preset cache area has cached data that a read target address points to when receiving a read...
2017/0286305 Prefetch command optimization for tiered storage systems
A system is provided. The system includes a storage controller configured to receive a prefetch command from a host interface. The storage controller includes...
2017/0286304 Pipelined Prefetcher for Parallel Advancement Of Multiple Data Streams
A processor includes a front end to decode instructions, an execution unit to execute instructions, multiple caches at different cache hierarchy levels, a...
2017/0286303 PREFETCH MECHANISM FOR SERVICING DEMAND MISS
Systems and methods relate to servicing a demand miss for a cache line in a first cache (e.g., an L1 cache) of a processing system, for example, when none of...
2017/0286302 HARDWARE APPARATUSES AND METHODS FOR MEMORY PERFORMANCE MONITORING
Methods and apparatuses relating to memory performance monitoring are described. In one embodiment, a processor includes at least one core, a performance...
2017/0286301 METHOD, SYSTEM, AND APPARATUS FOR A COHERENCY TASK LIST TO MINIMIZE CACHE SNOOPING BETWEEN CPU AND FPGA
Method and system implementing a task list in a cache agent for reducing cache line snoops. One embodiment comprises: monitoring a list of tasks that is stored...
2017/0286300 APPARATUS AND METHOD FOR LOW-OVERHEAD SYNCHRONOUS PAGE TABLE UPDATES
An apparatus and method are described for low overhead synchronous page table updates. For example, one embodiment of a processor comprises: a set of one or...
2017/0286299 SHARING AWARE SNOOP FILTER APPARATUS AND METHOD
An apparatus and method are described for a sharing aware snoop filter. For example, one embodiment of a processor comprises: a plurality of caches, each of...
2017/0286298 Implementation of Reserved Cache Slots in Computing System Having Inclusive/Non Inclusive Tracking And Two...
Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory...
2017/0286297 PERSISTENT MEMORY VERSIONING AND MERGING
Example implementations may relate to a version controller allocating a copy page in persistent memory upon receiving, from an application executing on a...
2017/0286296 MANAGING SYNONYMS IN VIRTUAL-ADDRESS CACHES
A virtual-address cache module receives at least a portion of a virtual address and in response indicates a hit or a miss. A first cache structure stores only...
2017/0286295 APPARATUS AND METHOD FOR TRIGGERED PREFETCHING TO IMPROVE I/O AND PRODUCER-CONSUMER WORKLOAD EFFICIENCY
An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first...
2017/0286294 APPARATUS, SYSTEM AND METHOD FOR CACHING COMPRESSED DATA
Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems,...
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