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Patent # Description
2017/0294392 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A method for fabricating a semiconductor structure includes providing a wafer and a carrier wafer. The wafer includes a first bonding surface and a plurality...
2017/0294391 DICING TECHNIQUES FOR POWER TRANSISTORS
Some embodiments relate to a die that has been formed by improved dicing techniques. The die includes a substrate which includes upper and lower substrate...
2017/0294390 LENS CAP FOR A TRANSISTOR OUTLINE PACKAGE
A lens cap for a transistor outline (TO) package is provided that has an inner diameter of less than 4 mm. The lens cap includes a metal shell with a wall...
2017/0294389 SEMICONDUCTOR PACKAGE STRUCTURE, PACKAGE ON PACKAGE STRUCTURE AND PACKAGING METHOD
A semiconductor package structure includes a substrate, a first semiconductor device, a first encapsulant and a second encapsulant. The substrate has a first...
2017/0294388 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction...
2017/0294387 ELECTRONIC CIRCUIT PACKAGE
Disclosed herein is an electronic circuit package includes a substrate having a power supply pattern, a first electronic component mounted on a first region of...
2017/0294386 FIELD-EFFECT TRANSISTOR, METHOD OF MANUFACTURING THE SAME, AND RADIO-FREQUENCY DEVICE
There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate...
2017/0294385 SEMICONDUCTOR STRUCTURES WITH FIELD EFFECT TRANSISTOR(S) HAVING LOW-RESISTANCE SOURCE/DRAIN CONTACT(S)
Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low...
2017/0294384 SEMICONDUCTOR STRUCTURE HAVING ETCHING STOP LAYER AND MANUFACTURING METHOD OF THE SAME
A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a stack structure, an etching stop layer,...
2017/0294383 SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES, AND RELATED METHODS AND ELECTRONIC SYSTEMS
A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at...
2017/0294382 SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS
Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first...
2017/0294381 SEMICONDUCTOR INTERCONNECT STRUCTURE WITH DOUBLE CONDUCTORS
Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first...
2017/0294380 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method...
2017/0294379 METHOD FOR FORMING AN ELECTRICAL CONTACT BETWEEN A SEMICONDUCTOR FILM AND A BULK HANDLE WAFER, AND RESULTING...
A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor...
2017/0294378 METHOD TO FABRICATE A HIGH PERFORMANCE CAPACITOR IN A BACK END OF LINE (BEOL)
A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the...
2017/0294377 MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICES INCLUDING VERTICALLY SHARED SOURCE LINES AND METHOD OF MAKING THEREOF
A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first...
2017/0294376 Reliable packaging and interconnect structures
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an...
2017/0294375 MEMORY CELL UNIT ARRAY
In a memory cell unit array, memory cell units each constituted of first wires, second wires, and a nonvolatile memory cell are arranged in a two-dimensional...
2017/0294374 ELECTRONIC PART MOUNTING HEAT-DISSIPATING SUBSTRATE
An electronic part mounting heat-dissipating substrate which includes: a conductor plate which is formed on lead frames of wiring pattern shapes; and an...
2017/0294373 ROBUST LOW INDUCTANCE POWER MODULE PACKAGE
A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality...
2017/0294372 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE
A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace...
2017/0294371 SEMICONDUCTOR PACKAGE AND A SUBSTRATE FOR PACKAGING
A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill...
2017/0294370 METHOD OF PRODUCING LEAD FRAMES FOR ELECTRONIC COMPONENTS, CORRESPONDING COMPONENT AND COMPUTER PROGRAM PRODUCT
An electronic component, in one embodiment, includes a semiconductor die, a die pad supporting the semiconductor die, and a plurality of leads that include a...
2017/0294369 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first...
2017/0294368 SEMICONDUCTOR DEVICE
A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first...
2017/0294367 Flat No-Leads Package With Improved Contact Pins
According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a...
2017/0294366 METHOD FOR MONITORING A HEAT EXCHANGER UNIT
Embodiments of the disclosure pertain to a method for monitoring a heat exchanger unit that may include the steps of: coupling the heat exchanger unit with a...
2017/0294365 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor element disposed on a semiconductor substrate; a first insulating film disposed on the semiconductor...
2017/0294363 FORMATION OF GETTER LAYER FOR MEMORY DEVICE
A method includes providing a semiconductor device disposed on a substrate, wherein the semiconductor device includes a semiconductor device feature, forming a...
2017/0294362 SEMICONDUCTOR PACKAGE WITH ELASTIC COUPLER AND RELATED METHODS
Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the...
2017/0294361 LID ARRAY PANEL, PACKAGE WITH LID AND METHOD OF MAKING THE SAME
A lid array panel includes multiple lids, where each lid includes an outer side wall. The lid array panel further includes a bridge section surrounding and...
2017/0294360 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including an interconnection structure provided on a cell region of a substrate to include a first line and a second line...
2017/0294359 SEMICONDUCTOR DEVICE INCLUDING A FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first...
2017/0294358 STACKED NANOWIRE DEVICES
A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is...
2017/0294357 CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES
Nanosheet semiconductor devices and methods of forming the same include forming a first stack in a first device region, the first stack including layers of a...
2017/0294356 FIN FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
A fin field-effect transistor is provided. The fin field-effect transistor includes a substrate, a fin structure, a gate-stacked structure, and an isolation...
2017/0294355 SEMICONDUCTOR DEVICES INCLUDING ACTIVE FINS AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins...
2017/0294354 INTEGRATION OF NOMINAL GATE WIDTH FINFETS AND DEVICES HAVING LARGER GATE WIDTH
A starting semiconductor structure includes a layer of filler material (e.g., amorphous silicon), a hard mask layer over the layer of filler material, and...
2017/0294353 METHOD OF MANUFACTURING PACKAGED WAFER
Disclosed herein is a method of manufacturing a packaged wafer including a step of forming grooves in a face side of a wafer along projected dicing lines to a...
2017/0294352 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to...
2017/0294351 ELECTRICAL CONDUCTIVE VIAS IN A SEMICONDUCTOR SUBSTRATE AND A CORRESPONDING MANUFACTURING METHOD
A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure...
2017/0294350 GATE ALIGNED CONTACT AND METHOD TO FABRICATE SAME
Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes...
2017/0294349 TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal...
2017/0294348 METHODS FOR FORMING 2-DIMENSIONAL SELF-ALIGNED VIAS
A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the...
2017/0294347 TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal...
2017/0294346 METHOD FOR REDUCING CONTACT RESISTANCE
Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure...
2017/0294345 METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided are a method and an apparatus for manufacturing a semiconductor device. The method comprises: forming a first wiring layer on a base substrate;...
2017/0294344 SEMICONDUCTOR DEVICE MANUFACTURING METHOD, COATING FORMATION METHOD, AND COATING FORMATION DEVICE
In the present method, a substrate to be processed, having an interlayer insulation film, is prepared (step 1). The interlayer insulation film is subjected to...
2017/0294343 ETCHING METHOD AND FABRICATION METHOD OF SEMICONDUCTOR STRUCTURES
An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure,...
2017/0294342 Structure and Method for Interconnection
Various self-aligned interconnect structures are disclosed herein. An exemplary interconnect structure includes a first dielectric layer disposed over a...
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