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Patent # Description
2017/0338348 FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES
Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface...
2017/0338347 SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS
A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device...
2017/0338346 SACRIFICIAL EPITAXIAL GATE STRESSORS
A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a sacrificial...
2017/0338345 SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to...
2017/0338344 SUBSTANTIALLY DEFECT FREE RELAXED HETEROGENEOUS SEMICONDUCTOR FINS ON BULK SUBSTRATES
A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a...
2017/0338343 HIGH-VOLTAGE TRANSISTOR DEVICE
A semiconductor device is provided comprising a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on...
2017/0338342 METHOD OF FORMING SEMICONDUCTOR DEVICE WITH GATE
A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation...
2017/0338341 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductor substrate comprising two source/drain regions,...
2017/0338340 SEMICONDUCTOR DEVICE
A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a first metal film...
2017/0338339 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the...
2017/0338338 Semiconductor Devices and Method for Manufacturing Semiconductor Devices
A method for manufacturing a semiconductor device includes: forming a recess in a semiconductor substrate, the recess having a bottom and a sidewall extending...
2017/0338337 DEVICE STRUCTURE HAVING INTER-DIGITATED BACK TO BACK MOSFETS
A bi-directional switch device includes two inter-digitated back-to-back vertical metal oxide semiconductor field effect transistors (MOSFETs) formed on a...
2017/0338336 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body...
2017/0338335 HIGH-SPEED DIODE AND METHOD FOR MANUFACTURING THE SAME
A high-speed diode includes an n-type semiconductor layer and a p-type semiconductor layer which is laminated on the n-type semiconductor layer, where a pn...
2017/0338334 VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT
A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a...
2017/0338333 NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is...
2017/0338332 Damage-Free Plasma-Enhanced CVD Passivation of AlGaN/GaN High Electron Mobility Transistors
Passivated AlGaN/GaN HEMTs having no plasma damage to the AlGaN surface and methods for making the same. In a first embodiment, a thin HF SiN barrier layer is...
2017/0338331 ENERGY-FILTERED COLD ELECTRON DEVICES AND METHODS
Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through...
2017/0338330 Method Of Making Split Gate Non-volatile Flash Memory Cell
A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in...
2017/0338329 INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER
Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich...
2017/0338328 METHOD OF FORMING INTERNAL DIELECTRIC SPACERS FOR HORIZONTAL NANOSHEET FET ARCHITECTURES
A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on...
2017/0338327 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof, the semiconductor device includes two gate structures and an epitaxial structure. The two gate...
2017/0338326 Two-Step Dummy Gate Formation
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions. A portion of the semiconductor...
2017/0338325 METHOD, APPARATUS AND SYSTEM FOR PROVIDING NITRIDE CAP LAYER IN REPLACEMENT METAL GATE STRUCTURE
We disclose a semiconductor device, comprising a semiconductor substrate; at least one gate structure disposed above the semiconductor substrate, wherein the...
2017/0338324 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating...
2017/0338323 DUMMY DIELECTRIC FINS FOR FINFETS WITH SILICON AND SILICON GERMANIUM CHANNELS
A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor...
2017/0338322 DUMMY DIELECTRIC FINS FOR FINFETS WITH SILICON AND SILICON GERMANIUM CHANNELS
A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor...
2017/0338321 NICKEL SILICIDE IMPLEMENTATION FOR SILICON-ON-INSULATOR (SOI) RADIO FREQUENCY (RF) SWITCH TECHNOLOGY
A radio frequency (RF) switch includes a plurality of series-connected silicon-on-insulator (SOI) CMOS transistors fabricated using a 0.13 micron (or larger)...
2017/0338320 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion...
2017/0338319 Methods and Structures of Novel Contact Feature
A method of fabricating a semiconductor device is disclosed. The method includes forming a fin structure on a substrate; forming a dummy gate over the fin...
2017/0338318 Method for Silicide Formation
Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device,...
2017/0338317 SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND...
A semiconductor device including a semiconductor substrate including a plurality of active regions and a device isolation region for isolating the plurality of...
2017/0338316 High Electron Mobility Transistor Structure and Method of Making the Same
A transistor includes a first layer over a substrate. The transistor also includes a second layer over the first layer. The transistor further includes a...
2017/0338315 COMPOSITE OXIDE SEMICONDUCTOR AND TRANSISTOR
A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region...
2017/0338314 ELECTRIC FIELD SHIELDING IN SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICE CELLS USING BODY REGION...
The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter...
2017/0338313 ELECTRIC FIELD SHIELDING IN SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICE CELLS
The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter...
2017/0338312 DIRECT TRANSFER OF MULTIPLE GRAPHENE LAYERS ONTO MULTIPLE TARGET SUBSTRATES
Disclosed is a method of making a conductive material or active material that includes graphene or other 2-D materials. The method includes obtaining a layered...
2017/0338311 GRAPHENE NMOS TRANSISTOR USING NITROGEN DIOXIDE CHEMICAL ADSORPTION
An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon....
2017/0338310 MOS TRANSISTOR FOR RADIATION-TOLERANT DIGITAL CMOS CIRCUITS
A monolithically integrated MOS transistor, comprising a doped well region of a first conductivity type, an active MOS transistor region formed in the well...
2017/0338309 POWER MOSFET
A power MOSFET includes a substrate, a semiconductor layer, a first gate, a second gate, a thermal oxide layer, a first CVD oxide layer, and a gate oxide...
2017/0338308 DIGITAL ALLOY VERTICAL LAMELLAE FINFET WITH CURRENT FLOW IN ALLOY LAYER DIRECTION
After forming semiconductor fins including vertically oriented alternating first digital alloy sublayer portions comprised of SiGe and second digital alloy...
2017/0338307 NANOTUBE SEMICONDUCTOR DEVICES
Semiconductor devices includes a thin epitaxial layer (nanotube) formed on sidewalls of mesas formed in a semiconductor layer. In one embodiment, a...
2017/0338306 Method for Manufacturing a Power Semiconductor Device
A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second...
2017/0338305 Structure and Method for Mitigating Substrate Parasitics in Bulk High Resistivity Substrate Technology
A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high...
2017/0338304 SEMICONDUCTOR DEVICE HAVING SELF-ISOLATING BULK SUBSTRATE AND METHOD THEREFOR
A semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second...
2017/0338303 ELECTRIC FIELD SHIELDING IN SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICES HAVING AN OPTIMIZATION LAYER
The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use...
2017/0338302 Power Semiconductor Device with Charge Balance Design
A semiconductor body having first and second vertically spaced apart surfaces is formed. A gate trench that vertically extends from the first surface of the...
2017/0338301 EDGE TERMINATION DESIGNS FOR SUPER JUNCTION DEVICE
This invention discloses a semiconductor power device formed on an upper epitaxial layer of a first conductivity type supported on a semiconductor substrate...
2017/0338300 ELECTRIC FIELD SHIELDING IN SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICE CELLS USING CHANNEL REGION...
The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter...
2017/0338299 ADAPTIVE CAPACITORS WITH REDUCED VARIATION IN VALUE AND IN-LINE METHODS FOR MAKING SAME
A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom...
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