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Patent # Description
2017/0338196 INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME
An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution...
2017/0338195 Antennas and Waveguides in InFO Structures
A method includes forming a first metal plate, forming a metal ring aligned to peripheral regions of the first metal plate, and placing a device die level with...
2017/0338194 HIGH-POWER AMPLIFIER PACKAGE
Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry...
2017/0338193 POWER SEMICONDUCTOR MODULE WITH SHORT-CIRCUIT FAILURE MODE
A description is given of a power semiconductor module 10 which can be transferred from a normal operating mode to an explosion-free robust short-circuit...
2017/0338192 METHOD OF FORMING METAL INTERCONNECTION AND METHOD OF FABRICATING SEMICONDUCTOR APPARATUS USING THE METHOD
A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in...
2017/0338191 THROUGH SILICON VIA CHIP AND MANUFACTURING METHOD THEREOF, FINGERPRINT IDENTIFICATION SENSOR AND TERMINAL DEVICE
A through silicon via chip and manufacturing method thereof are provided, where the through silicon via chip includes a silicon substrate, the silicon...
2017/0338190 POWER MODULE
A power module of the invention includes a power semiconductor element mounted on a circuit board, and an adapter connected to a front-surface main electrode...
2017/0338189 INSULATED CIRCUIT BOARD, POWER MODULE AND POWER UNIT
An insulated circuit board includes an insulated substrate, a first electrode, and a second electrode. A thin portion is formed in a corner portion, the corner...
2017/0338188 METHOD OF FABRICATING A POST-PASSIVATION INTERCONNECT STRUCTURE
A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure...
2017/0338187 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair...
2017/0338186 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded...
2017/0338185 Semiconductor Device and Method of Manufacture
A device comprising a semiconductor device, a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and...
2017/0338184 METHOD OF DICING INTEGRATED CIRCUIT WAFERS
A method of dicing an integrated circuit wafer by partially sawing the scribe street from the backside of the wafer and then completing sawing the scribe...
2017/0338183 MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor package includes the follow steps. Firstly, a carrier is provided. Then, a package substrate is formed. Then, a first...
2017/0338182 GLASS ARTICLES WITH NON-PLANAR FEATURES AND ALKALI-FREE GLASS ELEMENTS
An electronic device assembly includes a backplane having a glass composition substantially free of alkali ions, an elastic modulus of about 40 GPa to about...
2017/0338181 Integrated Circuit Structures Comprising Conductive Vias And Methods Of Forming Conductive Vias
A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first...
2017/0338180 METHOD OF MAKING VERTICAL AND BOTTOM BIAS E-FUSES AND RELATED DEVICES
A method for producing semiconductor devices including an electrical fuse (e-fuse) and the resulting device are provided. Embodiments include forming a gate...
2017/0338179 DEVICE PACKAGE WITH WIRE BOND ASSISTED GROUNDING AND INDUCTORS
Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the...
2017/0338178 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE HAVING CONDUCTIVE STRUCTURE WITH TWIN BOUNDARIES
A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes...
2017/0338177 Packaged Semiconductor Devices and Packaging Devices and Methods
Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes...
2017/0338176 SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SEMICONDUCTOR MODULE
An object of the invention is to manufacture a semiconductor module small. A metal wire (212) connecting a control electrode (101) and a control terminal (21)...
2017/0338175 SEMICONDUCTOR PACKAGE ASSEMBLY
The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure...
2017/0338174 PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME
A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the...
2017/0338173 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of...
2017/0338172 MULTILAYER SUBSTRATE, COMPONENT MOUNTED BOARD, AND METHOD FOR PRODUCING COMPONENT MOUNTED BOARD
A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal...
2017/0338171 Semiconductor Package Including Flip Chip Mounted IC and Vertically Integrated Inductor
In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second...
2017/0338170 SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK
Embodiments of the present disclosure are directed to flat no-lead packages with wettable sidewalls or flanks. In particular, wettable conductive layers are...
2017/0338169 CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT
In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically...
2017/0338168 SIGNAL BLOCK AND DOUBLE-FACED COOLING POWER MODULE USING THE SAME
A signal block and a double-faced cooling power module that uses the signal block is provided. The signal block includes a plurality of signal clips that are...
2017/0338167 HIGH PERFORMANCE TWO-PHASE COOLING APPARATUS FOR PORTABLE APPLICATIONS
The present application discloses two-phase cooling devices that may include at least three substrates: a metal with a wicking structure, an intermediate...
2017/0338166 STRUCTURE, AND ELECTRONIC COMPONENT AND ELECTRONIC DEVICE INCLUDING THE STRUCTURE
Provided herein is a structure having desirable heat dissipation, particularly a structure having high far-infrared emissivity. An electronic component...
2017/0338165 CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE
In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically...
2017/0338164 CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE
In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically...
2017/0338163 FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF
A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various...
2017/0338162 POWER MODULE WITH LOW STRAY INDUCTANCE
A power module providing a half bridge comprises at least one substrate and an inner metallization area, two intermediate metallization areas and two outer...
2017/0338161 COPPER FLANGED AIR CAVITY PACKAGES FOR HIGH FREQUENCY DEVICES
An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal....
2017/0338160 METHOD AND APPARATUS FOR DETERMINING PROCESS RATE
A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed,...
2017/0338159 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1...
2017/0338158 METHOD OF EVALUATING GETTERING PROPERTY
A gettering property evaluating method for a wafer includes: a gettering layer forming step of polishing a back surface opposite to a front surface of a...
2017/0338157 METHOD FOR PRODUCING ON THE SAME TRANSISTORS SUBSTRATE HAVING DIFFERENT CHARACTERISTICS
A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one...
2017/0338156 APPARATUS AND METHOD OF ADJUSTING WORK-FUNCTION METAL THICKNESS TO PROVIDE VARIABLE THRESHOLD VOLTAGES IN FINFETS
A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array...
2017/0338155 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of...
2017/0338154 FAN-OUT WAFER LEVEL CHIP PACKAGE STRUCTURE
A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate...
2017/0338153 Semiconductor Device and Methods for Forming a Plurality of Semiconductor Devices
A method for forming a plurality of semiconductor devices includes forming a plurality of trenches extending from a first lateral surface of a semiconductor...
2017/0338152 SOLDER FILL INTO HIGH ASPECT THROUGH HOLES
A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores...
2017/0338151 METHOD OF FORMING INTERCONNECT STRUCTURES BY SELF-ALIGNED APPROACH
A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask...
2017/0338150 Methods for Hybrid Wafer Bonding Integrated with CMOS Processing
Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated...
2017/0338149 SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
A method of fabricating a semiconductor device includes: forming a trench on an insulating layer to expose a first conductive feature disposed under the...
2017/0338148 DECOUPLED VIA FILL
Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls...
2017/0338147 Method of Forming Trenches
A method of forming a semiconductor device includes forming a material layer over a substrate and forming a first trench in the material layer, forming a...
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