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Patent # Description
2017/0337994 VALVE ASSEMBLY WITH ISOLATION VALVE VESSEL
Apparatuses for reducing or eliminating Type 1 LOCAs in a nuclear reactor vessel. A nuclear reactor including a nuclear reactor core comprising a fissile...
2017/0337993 Fuel Assembly
It is possible to achieve self-support of the fuel assembly without an upper grid plate when the fuel assembly is mounted or replaced, and it is also possible...
2017/0337992 SMALL, FAST NEUTRON SPECTRUM NUCLEAR POWER PLANT WITH A LONG REFUELING INTERVAL
Nuclear reactor systems and methods are described having many unique features tailored to address the special conditions and needs of emerging markets. The...
2017/0337991 SYSTEMS AND METHODS FOR MERGING AND COMPRESSING COMPACT TORI
Systems and methods utilizing successive, axially symmetric acceleration and adiabatic compression stages to heat and accelerate two compact tori towards each...
2017/0337990 APPARATUS FOR MAGNETIC AND ELECTROSTATIC CONFINEMENT OF PLASMA
A system and method for containing plasma and forming a Field Reversed Configuration (FRC) magnetic topology are described in which plasma ions are contained...
2017/0337989 REACTOR USING ELECTRICAL AND MAGNETIC FIELDS
Methods, apparatuses, devices, and systems for producing and controlling and fusion activities of nuclei. Hydrogen atoms or other neutral species (neutrals)...
2017/0337988 Test Apparatus Based on Binary Vector
A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a...
2017/0337987 SELF-TESTING A STORAGE DEVICE VIA SYSTEM MANAGEMENT BUS INTERFACE
A system and method are provided for self-testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more...
2017/0337986 SEMICONDUCTOR MEMORY DEVICE AND WEAK CELL DETECTION METHOD THEREOF
A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the...
2017/0337985 SINGLE CIRCUIT ONE-TIME PROGRAMMABLE MEMORY AND VOLATILE MEMORY
A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating...
2017/0337984 DRAM RETENTION TEST METHOD FOR DYNAMIC ERROR CORRECTION
A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory...
2017/0337983 FAST MAGNETOELECTRIC DEVICE BASED ON CURRENT-DRIVEN DOMAIN WALL PROPAGATION
In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE...
2017/0337982 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of...
2017/0337981 NON-VOLATILE MEMORY DEVICES AND METHODS OF OPERATING THE SAME
A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND...
2017/0337980 Flash Memory Array With Individual Memory Cell Read, Program And Erase
A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory...
2017/0337979 OPERATING METHOD OF MEMORY CONTROLLER CONTROLLING NON-VOLATILE MEMORY DEVICE PERFORMING REFRESH READ OPERATION
An operating method of a memory controller, configured to control a non-volatile memory device that performs a refresh read operation, detects a power on state...
2017/0337978 Flash Memory Cell And Associated Decoders
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The...
2017/0337977 STORAGE CONTROL DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM
A storage control device includes a determination unit configured to determine whether each area in a nonvolatile storage is set to be in a partition...
2017/0337976 SEMICONDUCTOR DEVICE
A semiconductor device includes a memory circuit, a first FIFO, a second FIFO and an input/output circuit. The memory circuit outputs data. The first FIFO...
2017/0337975 LOW VOLTAGE DETECTION CIRCUIT, NONVOLATILE MEMORY APPARATUS INCLUDING THE SAME, AND OPERATING METHOD THEREOF
A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and...
2017/0337974 RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES
Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected...
2017/0337973 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a...
2017/0337972 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system may include a memory device including a plurality of memory blocks each memory block including a plurality of pages; and a controller suitable...
2017/0337971 Array of Three-Gate Flash Memory Cells With Individual Memory Cell Read, Program and Erase
A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and...
2017/0337969 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
A semiconductor memory device includes a plurality of memory cells, a plurality of word lines, including a word line that is connected to a group of the memory...
2017/0337968 Method for Implementing Memristive Logic Gates
An embodiment of the present invention provides a method for implementing Boolean functionality to create AND, OR, NAND, NOR, or NOT logic gates using a single...
2017/0337967 MEMORY DEVICES AND METHODS FOR OPERATING THE SAME
A memory device includes a memory including memory cells, each of the memory cells being configured to store multiple bits of data. The memory device includes...
2017/0337966 MEMORY DEVICE SHARED BY TWO OR MORE PROCESSORS AND SYSTEM INCLUDING THE SAME
A common memory device shared by a first processor and a second processor is provided. The common memory device includes a memory cell array including a first...
2017/0337965 Memory Systems and Methods for Improved Power Management
A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each...
2017/0337964 Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers...
2017/0337963 LIGHT EMITTING ELEMENT DRIVING SEMICONDUCTOR INTEGRATED CIRCUIT, LIGHT EMITTING ELEMENT DRIVING DEVICE, LIGHT...
A light emitting element driving semiconductor integrated circuit constitutes at least a part of a light emitting element driving device arranged to drive a...
2017/0337962 ADAPTIVE REFRESHING AND READ VOLTAGE CONTROL SCHEME FOR A MEMORY DEVICE SUCH AS AN FeDRAM
A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g.,...
2017/0337961 ELECTRONIC DEVICE
An electronic device may include a semiconductor memory. The semiconductor memory may include a global line pair including a global bit line and a global...
2017/0337960 SENSE PATH CIRCUITRY SUITABLE FOR MAGNETIC TUNNEL JUNCTION MEMORIES
A memory includes a first memory cell; and a second memory cell. A selectable current path is coupled between the first memory cell and the second memory cell....
2017/0337959 NONVOLATILE LOGIC AND SECURITY CIRCUITS
In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For...
2017/0337958 BITCELL STATE RETENTION
In accordance with various embodiments of this disclosure, stray magnetic field mitigation in an MRAM memory such as a spin transfer torque (STT) random access...
2017/0337957 METHOD AND SYSTEM FOR POWER SIGNATURE SUPPRESSION IN MEMORY DEVICES
A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit,...
2017/0337956 NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR OPERATING SEMICONDUCTOR DEVICE
A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit...
2017/0337955 Active Random Access Memory
Systems and methods for processing commands at a random access memory. A series of commands are received to read data from the random access memory or to write...
2017/0337954 APPARATUSES AND METHODS FOR SHIFTING DATA
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and...
2017/0337953 APPARATUSES AND METHODS FOR SCATTER AND GATHER
The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that...
2017/0337952 Dual-Range Clock Duty Cycle Corrector
Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock...
2017/0337951 APPARATUSES AND METHODS FOR PERFORMING INTRA-MODULE DATABUS INVERSION OPERATIONS
Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module...
2017/0337950 SEMICONDUCTOR MEMORY APPARATUS AND OPERATING METHOD
A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line...
2017/0337949 MOBILE DEVICE VIDEO PERSONALIZATION
The disclosure includes embodiments for generating a synched video. A method includes determining a duration and a number of discrete frames of an original...
2017/0337948 Marking Media Files
Methods, systems, and products insert markers into recorded media modules. A pair of reference points is received that marks a position and another position in...
2017/0337947 Friction Adjustment Mechanisms for Optimizing Friction Between a Pad and a Disc in an Optical Disc Restoration...
The invention pertains in general to a latching mechanism for maintaining desired friction levels on an optical disc in an optical disc restoration device. In...
2017/0337946 RECORDING MEDIUM, PLAYBACK DEVICE, AND PLAYBACK METHOD
A playback device is provided that includes a readout unit that reads out data recorded in a recording medium and a playback unit. Data including a digital...
2017/0337945 MAGNETIC RECORDING MEDIUM AND MAGNETIC RECORDING/REPRODUCING APPARATUS
The present invention relates to a magnetic recording medium in which a lubricant layer contains a compound A represented by general formula (1) and a compound...
2017/0337944 PROTECTIVE LAYER FOR MITIGATING PROTRUDING DEFECTS IN MAGNETIC TAPE RECORDING MEDIA
A magnetic recording medium according to one embodiment includes an underlayer and a magnetic layer above the underlayer. The magnetic layer includes a first...
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