Easy To Use Patents Search & Patent Lawyer Directory
At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Searching:
Search by keyword, patent number, inventor, assignee, city or state:
| Patent # | Description |
|---|---|
| 2017/0345845 |
ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME An array substrate, and a display panel and display device including the same are disclosed. An embodiment of the array substrate comprises a display region... |
| 2017/0345844 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Provided herein is a semiconductor device including N stacked groups (where N is a natural number greater than or equal to two) sequentially stacked over a... |
| 2017/0345843 |
VERTICAL MEMORY DEVICES A vertical memory device includes a plurality of stacked structures, at least one inter-structure layer, and a channel structure. The plurality of stacked... |
| 2017/0345842 |
SEMICONDUCTOR DEVICE A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of... |
| 2017/0345841 |
NVM MEMORY HKMG INTEGRATION TECHNOLOGY The present disclosure relates to a method of forming an integrated circuit (IC). In some embodiments, a substrate is provided comprising a memory region and a... |
| 2017/0345840 |
Method Of Integrating FINFET CMOS Devices With Embedded Nonvolatile Memory
Cells A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions,... |
| 2017/0345839 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device includes channel layers arranged in a first direction and a second direction intersecting the first direction; stacked insulating layers... |
| 2017/0345838 |
NON-VOLATILE MEMORY DEVICE According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive... |
| 2017/0345837 |
SEMICONDUCTOR MEMORY DEVICE A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and... |
| 2017/0345836 |
Method for Forming a PN Junction and Associated Semiconductor Device A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity... |
| 2017/0345835 |
SELF-ALIGNED FLASH MEMORY DEVICE The present disclosure relates to an improved integrated circuit having an embedded flash memory device with a word line having its height reduced, and... |
| 2017/0345834 |
SOI MEMORY DEVICE A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a... |
| 2017/0345833 |
METHOD OF MANUFACTURING AND OPERATING A NON-VOLATILE MEMORY CELL A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second... |
| 2017/0345832 |
NVM Memory HKMG Integration Technology The present disclosure relates to an integrated circuit (IC) that includes a HKMG hybrid non-volatile memory (NVM) device and that provides small scale and... |
| 2017/0345831 |
Ferroelectric Devices and Methods of Forming Ferroelectric Devices Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor ... |
| 2017/0345830 |
LOW POWER EMBEDDED ONE-TIME PROGRAMMABLE (OTP) STRUCTURES Devices and methods for forming a device are presented. The method includes providing a substrate prepared with at least a first region for accommodating an... |
| 2017/0345829 |
HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate;... |
| 2017/0345828 |
Non-volatile memory and method for programming and reading a memory array
having the same A non-volatile memory (NVM) includes a fin structure, a first fin field effect transistor (FinFET), a second FinFET, an antifuse structure, a third FinFET, and... |
| 2017/0345827 |
Double Metal Layout for Memory Cells of a Non-Volatile Memory A non-volatile memory having a double metal layout is provided that includes a first fuse fabricated on a first conductive layer of the integrated circuit, a... |
| 2017/0345826 |
METHOD FOR PRODUCING PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE A method for producing a pillar-shaped semiconductor memory device includes forming a mask on a semiconductor substrate and etching to form a semiconductor... |
| 2017/0345825 |
SEMICONDUCTOR DEVICES INCLUDING A DUMMY GATE STRUCTURE ON A FIN Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The... |
| 2017/0345824 |
Methods of Fabricating Semiconductor Devices A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the... |
| 2017/0345823 |
ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME An electronic device includes a semiconductor memory. The semiconductor memory may include a semiconductor substrate having an isolation trench in a first... |
| 2017/0345822 |
SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of... |
| 2017/0345821 |
HIGH SPEED SEMICONDUCTOR DEVICE A semiconductor device includes a fin extending from a substrate, a first source/drain feature, a second source/drain feature, and a gate structure on the fin.... |
| 2017/0345820 |
Metal Gate Isolation Structure and Method Forming Same A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region... |
| 2017/0345819 |
SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE WITH REDUCED THRESHOLD VOLTAGE
AND METHOD FOR MANUFACTURING THE SAME A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and... |
| 2017/0345818 |
Semiconductor Devices with Trench Gate Structures in a Semiconductor Body
with Hexagonal Crystal Lattice A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is... |
| 2017/0345817 |
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR AND SEMICONDUCTOR
MODULE A semiconductor device of the present invention achieves improved avoidance of a parasitic operation in a circuit region while achieving miniaturization of the... |
| 2017/0345816 |
DECOUPLING CAPACITOR A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The... |
| 2017/0345815 |
THIN-FILM DEVICE A thin-film device is provided with high reliability that prevents breakage of a thin-film resistance element due to stress caused by expansion of a resin... |
| 2017/0345814 |
SEMICONDUCTOR DEVICE According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a... |
| 2017/0345813 |
LOW DYNAMIC RESISTANCE LOW CAPACITANCE DIODES A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5... |
| 2017/0345812 |
THROUGH VIA EXTENDING THROUGH A GROUP III-V LAYER A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed... |
| 2017/0345811 |
METHOD FOR MANUFACTURING ESD PROTECTION DEVICE Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a... |
| 2017/0345810 |
Semiconductor Devices With Cells Comprising Routing Resources A cell comprising at least one diffusion region and a plurality of interconnection conductive patterns located over the at least one diffusion layer and... |
| 2017/0345809 |
CIRCUIT WITH COMBINED CELLS AND METHOD FOR MANUFACTURING THE SAME In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the... |
| 2017/0345808 |
ELECTRIC POWER CONVERSION CIRCUIT INCLUDING SWITCHES AND BOOTSTRAP
CIRCUITS, AND ELECTRIC POWER TRANSMISSION... An electric power conversion circuit includes: first and second input terminals; first and second output terminals; first and third switches connected to the... |
| 2017/0345807 |
Multi-Stack Package-on-Package Structures A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die... |
| 2017/0345806 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE A semiconductor device includes a first substrate, an insulation layer, and a first electrode. The first substrate contains a first semiconductor material. The... |
| 2017/0345805 |
PACKAGE INCLUDING STACKED DIE AND PASSIVE COMPONENT Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A... |
| 2017/0345804 |
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the... |
| 2017/0345803 |
MODULE STACKING MECHANISM WITH INTEGRATED GROUND Printed circuit board (PCB) structures and methods of assembling them are described herein. In some embodiments, a PCB structure may include a first mounting... |
| 2017/0345802 |
DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION
METHOD THEREOF The present disclosure relates to a display device using a semiconductor light emitting device and a fabrication method thereof. A display device may include a... |
| 2017/0345801 |
DISPLAY APPARATUS AND FABRICATING METHOD THEREOF A display apparatus and a fabricating method thereof are provided. The display apparatus includes a substrate, a light emitting diode, a first bump, a first... |
| 2017/0345800 |
LED MODULE An LED module includes: a substrate having a main surface and a back surface which face in opposite directions from each other in a thickness direction; a... |
| 2017/0345799 |
POWER MODULE A power module may include a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a... |
| 2017/0345798 |
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME A semiconductor structure includes: a first semiconductor workpiece; a second semiconductor workpiece, bonded to a first surface of the first semiconductor... |
| 2017/0345797 |
SEMICONDUCTOR ADHESIVE, AND SEMICONDUCTOR DEVICE AND METHOD FOR
MANUFACTURING SAME A semiconductor adhesive used for sealing connection portions of a semiconductor device, wherein: in the semiconductor device, the connection portion of a... |
| 2017/0345796 |
ELECTRONIC DEVICE WITH STACKED ELECTRONIC CHIPS An electronic device includes a carrier substrate, a first electronic chip and a second chip. The first chip is mounted on the carrier substrate via interposed... |
File A Patent Application
- Protect your idea -- Don't let someone else file first. Learn more.
- 3 Easy Steps -- Complete Form, application Review, and File. See our process.
- Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.