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Patent # Description
2017/0365626 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable...
2017/0365625 DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND DRIVING METHOD THEREOF
An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor...
2017/0365624 SEMICONDUCTOR DEVICE
A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the...
2017/0365623 LOW-TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM TRANSISTOR, AND MANUFACTURING METHOD FOR FABRICATING THE...
Disclosed are a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), a method for fabricating the same, an array substrate, a display...
2017/0365622 ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE
An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate. A signal transmission line, first and second...
2017/0365621 Semiconductor Chip and Method for Manufacturing the Same
Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other...
2017/0365620 Semiconductor Chip and Method for Manufacturing the Same
Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate...
2017/0365619 MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the...
2017/0365618 SYSTEMS INCLUDING MEMORY CELLS ON OPPOSING SIDES OF A PILLAR
Systems including a processor and a memory device in communication with the processor include an array of non-volatile memory cells configured in a NAND...
2017/0365617 Integrated Structures and Methods of Forming Integrated Structures
Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A...
2017/0365616 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the...
2017/0365615 FLOATING GATE MEMORY CELLS IN VERTICAL MEMORY
Floating gate memory cells in vertical memory. A control gate is formed between a first tier of dielectric material and a second tier of dielectric material. A...
2017/0365614 CHARGE STORAGE APPARATUS AND METHODS
Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is...
2017/0365613 THREE-DIMENSIONAL MEMORY DEVICE HAVING EPITAXIAL GERMANIUM-CONTAINING VERTICAL CHANNEL AND METHOD OF MAKING THEREOF
An alternating stack of insulating layers and spacer material layers is formed over a semiconductor substrate. Memory openings are formed through the...
2017/0365612 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction...
2017/0365611 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and...
2017/0365610 FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EMBEDDED CAPACITOR
A method for forming a semiconductor device is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming a contact...
2017/0365609 Novel Compounds For Preventing And/Or Treating Lysosomal Storage Disorders And/Or Degenerative Disorders Of The...
Described are novel salts of the compound (3R,4R,5S)-5-(difluoromethyl) piperidine-3,4-diol, as well as methods of using the same for preventing and/or...
2017/0365608 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device...
2017/0365607 Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled...
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are...
2017/0365606 STRUCTURE AND METHOD TO PREVENT EPI SHORT BETWEEN TRENCHES IN FINFET EDRAM
After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench...
2017/0365605 NON-VOLATILE SCHOTTKY BARRIER FIELD EFFECT TRANSISTOR
The present disclosure generally relates to an apparatus for high density memory with integrated logic. A three terminal ReRAM device, which includes a p-n...
2017/0365604 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the...
2017/0365603 LDMOS FINFET DEVICE
A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the...
2017/0365602 LDMOS DESIGN FOR A FINFET DEVICE
A method of manufacturing a semiconductor device is provided. The device includes a substrate including a first type region and a second type region, first and...
2017/0365601 SEMICONDUCTOR DEVICE WITH DIFFERENT FIN PITCHES
A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second...
2017/0365600 Using Inter-Tier Vias in Integrated Circuits
Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a...
2017/0365599 HIGH-VOLTAGE SEMICONDUCTOR DEVICES
A high-voltage semiconductor device includes a MOS device and a resistor device. The MOS device has a source, a drain, a drain insulation region adjacent to...
2017/0365598 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
An HVIC is a gate driver IC that drives a three-phase inverter and includes high-potential-side regions for three phases on a single semiconductor substrate....
2017/0365597 Vertical Nanowire Transistor for Input/Output Structure
An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to...
2017/0365596 METHOD AND STRUCTURE FOR FORMING BURIED ESD WITH FINFETS
A semiconductor structure is provided that includes an electrostatic discharge (ESD) device integrated on the same semiconductor substrate as semiconductor fin...
2017/0365595 Schottky Integrated High Voltage Terminations and Related HVIC Applications
A Schottky diode includes a cathode terminal in a high voltage region of a semiconductor die, an anode terminal in a low voltage region of the semiconductor...
2017/0365594 INTEGRATED CIRCUIT
An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor...
2017/0365593 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the...
2017/0365592 LAYOUT METHOD FOR INTEGRATED CIRCUIT AND LAYOUT OF THE INTEGRATED CIRCUIT
A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting...
2017/0365591 SEMICONDUCTOR DEVICE HAVING STACKED SEMICONDUCTOR CHIPS AND METHOD FOR FABRICATING THE SAME
A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips...
2017/0365590 SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME
Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips...
2017/0365589 LIGHT-EMITTING APPARATUS
A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in...
2017/0365588 OPTOELECTRONIC SEMICONDUCTOR DEVICE
An optoelectronic semiconductor device includes an epitaxial substrate and a plurality of microsized optoelectronic semiconductor elements. The microsized...
2017/0365587 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME
The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged...
2017/0365586 Semiconductor Device on String Circuit and Method of Making the Same
An elongated light circuit includes an elongated circuit trace and a plurality of micro-sized, unpackaged LEDs disposed sequentially on the circuit trace. A...
2017/0365585 LED PACKAGE
An LED package having a plurality of light emitting regions includes a plurality of LED chips. The LED package further includes a plurality of electrode...
2017/0365584 SEMICONDUCTOR DEVICE ASSEMBLY WITH HEAT TRANSFER STRUCTURE FORMED FROM SEMICONDUCTOR MATERIAL
Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor...
2017/0365583 SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal...
2017/0365582 SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate, a plurality of semiconductor chips stacked on the substrate, and a plurality of bonding layers bonded to lower...
2017/0365581 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of...
2017/0365580 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
A semiconductor package may include a first logic die and a second logic die located laterally adjacent to the first logic die. A bridge memory die may be...
2017/0365579 3D CHIP-ON-WAFER-ON-SUBSTRATE STRUCTURE WITH VIA LAST PROCESS
Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL...
2017/0365578 DIE BONDING APPARATUS AND DIE BONDING METHOD
A die bonding apparatus includes: a mounting base including a mounting area on which a first member is mounted; a heater arranged below the mounting base; a...
2017/0365577 SEMICONDUCTOR DEVICE WITH A WIRE BONDING AND A SINTERED REGION, AND MANUFACTURING PROCESS THEREOF
An electronic device includes: a semiconductor body; a front metallization region; a top buffer region, arranged between the front metallization region and the...
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