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Patent # Description
2018/0053784 SYSTEM ON CHIP FULLY-DEPLETED SILICON ON INSULATOR WITH RF AND MM-WAVE INTEGRATED FUNCTIONS
A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is...
2018/0053783 SEMICONDUCTOR DEVICE
A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact...
2018/0053782 SEMICONDUCTOR MEMORY DEVICE INCLUDING 3-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device mc des a substrate defined with cell regions and a contact region between the cell regions; a dielectric structure formed over...
2018/0053781 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, the plurality of charge storage films are separated in a stacking direction with a second air gap interposed. The plurality of...
2018/0053780 SEMICONDUCTOR DEVICE
The present disclosure relates to a semiconductor device including a stress control insulating layer or a stress control pattern to control a stress applied to...
2018/0053779 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by...
2018/0053778 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a...
2018/0053777 METAL-ONO-VACUUM TUBE CHARGE TRAP FLASH (VTCTF) NONVOLATILE MEMORY AND THE METHOD FOR MAKING THE SAME
The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using ...
2018/0053776 MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A memory device is provided. The memory device includes a substrate and a first stack structure. The first stack structure includes a tunneling layer. The...
2018/0053775 Semiconductor Devices with Charge Fixing Layers
A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate...
2018/0053774 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage...
2018/0053773 INTEGRATION OF FLOATING GATE MEMORY AND LOGIC DEVICE IN REPLACEMENT GATE FLOW
After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second...
2018/0053772 MEMORY DEVICE HAVING INTERCHANGEABLE GATE/CHANNEL TRANSISTOR AND MANUFACTURING METHOD OF THE SAME
A memory device is provided. The memory device includes a bottom conductive line, a stacked structure, a side oxide layer, a dielectric layer and a side...
2018/0053771 SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a ...
2018/0053770 METHOD FOR FORMING BURIED BIT LINE, SEMICONDUCTOR DEVICE HAVING THE SAME, AND FABRICATING METHOD THEREOF
A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a...
2018/0053769 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using...
2018/0053768 VERTICAL MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel...
2018/0053767 VERTICAL ANTIFUSE STRUCTURES
Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical...
2018/0053766 High Density Vertical Thyristor Memory Cell Array with Improved Isolation
Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation...
2018/0053765 DUAL DEEP TRENCHES FOR HIGH VOLTAGE ISOLATION
A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a...
2018/0053764 PROCESS ENHANCEMENT USING DOUBLE SIDED EPITAXIAL ON SUBSTRATE
Disclosed examples include semiconductor devices and fabrication methods to fabricate semiconductor wafers and integrated circuits, including forming a first...
2018/0053763 Field Effect Transistor Contact with Reduced Contact Resistance
The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate...
2018/0053762 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes at least one semiconductor fin, a gate electrode, at least one gate spacer, and a gate dielectric. The semiconductor fin...
2018/0053761 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate including at least one fin structure is provided. A...
2018/0053760 SELF-BALANCED DIODE DEVICE
A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity...
2018/0053759 SEMICONDUCTOR DEVICE
A semiconductor device includes a first circuit configured to generate a current corresponding to the input signal, a second circuit configured to generate a...
2018/0053758 INTEGRATED DEVICE WITH P-I-N DIODES AND VERTICAL FIELD EFFECT TRANSISTORS
An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second...
2018/0053757 ASSIST CUTS DISPOSED IN DUMMY LINES TO IMPROVE METAL SIGNAL CUTS IN ACTIVE LINES OF A SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate....
2018/0053756 SEMICONDUCTOR DEVICE STRUCTURE
A semiconductor device structure includes a first chip including a plurality of dielectric layers and a multi-layered metal structure embedded in the plurality...
2018/0053755 POWER SWITCH PACKAGING WITH PRE-FORMED ELECTRICAL CONNECTIONS FOR CONNECTING INDUCTOR TO ONE OR MORE TRANSISTORS
In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the...
2018/0053754 LIGHT-EMITTING ELEMENT AND IMAGE DISPLAY DEVICE
A light-emitting element includes a casing that includes a recess, an LED chip disposed on a bottom surface of the recess of the casing, a sealing member to...
2018/0053753 STACKABLE MOLDED PACKAGES AND METHODS OF MANUFACTURE THEREOF
A stackable package assembly and method of manufacturing is provided. The method includes attaching a plurality of interconnect balls to a first surface of a...
2018/0053752 Apparatus for Multi-Direct Transfer of Semiconductors
An apparatus includes a frame to hold a wafer tape having a first side and a second side. A plurality of semiconductor device dies are disposed on the first...
2018/0053751 TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED
The present invention discloses a transferring method, a manufacturing method, a device and an electronics apparatus of micro-LED. The method for transferring...
2018/0053750 METHOD OF FABRICATING LIGHT EMITTING DIODE MODULE
A method of fabricating a LED module includes preparing a circuit board, such that the circuit board includes a reflective laminate around a chip mounting...
2018/0053749 APPARATUS AND METHODS FOR MULTI-DIE PACKAGING
A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of...
2018/0053748 Buffer Layer(s) on a Stacked Structure Having a Via
A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and...
2018/0053747 FAN-OUT PACKAGES INCLUDING VERTICALLY STACKED CHIPS AND METHODS OF FABRICATING THE SAME
A fan-out package may include a core supporter having a through hole, a first semiconductor chip disposed on a first surface of the core supporter in a way...
2018/0053746 SEMICONDUCTOR PACKAGES WITH THERMAL-ELECTRICAL-MECHANICAL CHIPS AND METHODS OF FORMING THE SAME
In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM...
2018/0053745 METHOD FOR FORMING A PACKAGE STRUCTURE INCLUDING FORMING A MOLDING COMPOUND ON FIRST LARGER BUMPS SURROUNDING A...
Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution...
2018/0053744 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device including semiconductor units 20A to 20C that each include semiconductor elements 12 and 13, a unit case 11 sealing the semiconductor...
2018/0053743 IC STRUCTURE ON TWO SIDES OF SUBSTRATE AND METHOD OF FORMING
An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active...
2018/0053742 METHOD OF MASS TRANSFERRING ELECTRONIC DEVICE
A method of mass transferring electronic devices includes following steps. A wafer is provided. The wafer includes a substrate and a plurality of electronic...
2018/0053741 BUMP STRUCTURE HAVING A SIDE RECESS AND SEMICONDUCTOR STRUCTURE INCLUDING THE SAME
In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate,...
2018/0053740 LAND GRID BASED MULTI SIZE PAD PACKAGE
The present disclosure provides packages and methods for fabricating packages. A package may comprise a wafer-level package (WLP) layer comprising first and...
2018/0053739 SEMICONDUCTOR WAFER AND METHOD OF BALL DROP ON THIN WAFER WITH EDGE SUPPORT RING
A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor...
2018/0053738 INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD
An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including...
2018/0053737 POWER SEMICONDUCTOR DEVICE
In a power semiconductor device, a front-surface electrode of a power semiconductor element is formed in such a manner that, on a first Cu layer consisting...
2018/0053736 CHIP PART
A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which...
2018/0053735 WIRELESS MODULE
A ground plane is provided to a dielectric board. A high-frequency integrated circuit element is mounted on the dielectric board. A shield member...
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