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Patent # Description
2018/0061992 VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of...
2018/0061991 Thin Film Transistor And Method of Manufacturing the Same, And Display Device
Embodiments of the present disclosure provide a thin film transistor and a method of manufacturing the same, and a display device. In an embodiment, the thin...
2018/0061990 ACTIVE LAYER, THIN FILM TRANSISTOR, ARRAY SUBSTRATE, AND DISPLAY APPARATUS AND FABRICATION METHODS
The present disclosure provides an active layer, a thin film transistor, an array substrate, and a display apparatus, and fabrication methods thereof. A method...
2018/0061989 SEMICONDUCTOR DEVICE
A high-performance semiconductor device with high reliability is provided. The semiconductor device includes a first transistor, a second transistor, a first...
2018/0061988 FETs and Methods for Forming the Same
FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and...
2018/0061987 FABRICATION OF SEMICONDUCTOR DEVICE
A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in...
2018/0061986 Structure and Method for Integrated Circuit
The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a...
2018/0061985 Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink - Harmonic...
A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and...
2018/0061984 SELF-BIASING AND SELF-SEQUENCING OF DEPLETION-MODE TRANSISTORS
A transistor circuit includes a transistor having a gate terminal and first and second conduction terminals, a first circuit configured to convert an AC input...
2018/0061983 SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer,...
2018/0061982 AN ELECTRONIC JUNCTION DEVICE WITH A REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT...
An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode...
2018/0061981 LATERALLY DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF
The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed...
2018/0061980 SEMICONDUCTOR DEVICE
A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first...
2018/0061979 Method of Manufacturing a Superjunction Semiconductor Device and Superjunction Semiconductor Device
A semiconductor device is manufactured in a semiconductor body of a wafer by forming a mask on a surface of the semiconductor body. The mask has a plurality of...
2018/0061978 HORIZONTAL GATE ALL AROUND AND FINFET DEVICE ISOLATION
Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor...
2018/0061977 DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A T-SHAPE IN THE METAL GATE LINE-END
A method of fabricating a metal gate structure in a semiconductor device is disclosed. The method comprises removing a dummy poly gate, removing IL oxide and...
2018/0061976 INTEGRATED CIRCUIT STRUCTURE WITHOUT GATE CONTACT AND METHOD OF FORMING SAME
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate...
2018/0061975 NITRIDE SEMICONDUCTOR DEVICE AND NITRIDE SEMICONDUCTOR PACKAGE
Provided is a nitride semiconductor device 3 including a GaN electron transit layer 13, an AlGaN electron supply layer 14 in contact with the electron transit...
2018/0061974 SEMICONDUCTOR DEVICE, POWER SUPPLY CIRCUIT, AND COMPUTER
A semiconductor device of an embodiment includes a nitride semiconductor layer, a first electrode provided on the nitride semiconductor layer, a second...
2018/0061973 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE COMPOUND SEMICONDUCTOR DEVICE
A disclosed compound semiconductor device includes a substrate, a channel layer formed over the substrate, an electron supply layer formed on the channel...
2018/0061972 REVERSE CONDUCTING IGBT
The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor...
2018/0061971 Transistor Device with High Current Robustness
A transistor device includes a first emitter region of a first doping type, a second emitter region of a second doping type, a body of the second doping type,...
2018/0061970 MAGNETIC MAJORITY GATE DEVICE
The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate...
2018/0061969 INTEGRATED CIRCUIT FABRICATION WITH BORON ETCH-STOP LAYER
Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich...
2018/0061968 CONTACT STRUCTURE AND EXTENSION FORMATION FOR III-V NFET
FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the...
2018/0061967 CLOSELY PACKED VERTICAL TRANSISTORS WITH REDUCED CONTACT RESISTANCE
A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a...
2018/0061966 COMPOSITE SPACER ENABLING UNIFORM DOPING IN RECESSED FIN DEVICES
A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial...
2018/0061965 REPLACEMENT METAL GATE STRUCTURES
Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method...
2018/0061964 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF
The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has...
2018/0061963 FABRICATING METHOD OF SEMICONDUCTOR STRUCTURE
A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask...
2018/0061961 METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR
Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises a step of providing a layer stack, the layer stack...
2018/0061960 SILICON CARBIDE SEMICONDUCTOR BASE, METHOD OF CRYSTAL AXIS ALIGNMENT IN SILICON CARBIDE SEMICONDUCTOR BASE, AND...
On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark...
2018/0061959 Purging Deposition Tools to Reduce Oxygen and Moisture in Wafers
A method includes placing a wafer in a wafer holder, placing the wafer holder on a loadport of a deposition tool, connecting the wafer holder to a front-end...
2018/0061958 METHODS OF FABRICATING SEMICONDUCTOR DEVICES
A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction...
2018/0061957 ATOMIC LAYER DEPOSITION METHODS AND STRUCTURES THEREOF
A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a...
2018/0061956 MASKLESS METHOD TO REDUCE SOURCE-DRAIN CONTACT RESISTANCE IN CMOS DEVICES
Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact...
2018/0061955 ALL-AROUND GATE FIELD-EFFECT TRANSISTOR
An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with...
2018/0061954 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device (100) includes a base layer (10), an interface layer (20), and a deposition layer (30). The base layer (10) includes a nitride...
2018/0061953 High Voltage Laterally Diffused MOSFET with Buried Field Shield and Method to Fabricate Same
A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in...
2018/0061952 CRYSTALLINE OXIDE SEMICONDUCTOR FILM, CRYSTALLINE OXIDE SEMICONDUCTOR DEVICE, AND CRYSTALLINE OXIDE...
In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a...
2018/0061951 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
A silicon carbide semiconductor device includes a first semiconductor layer of a first conductivity type provided on a front surface of a silicon carbide...
2018/0061950 TRANSISTOR DEVICE WITH THRESHOLD VOLTAGE ADJUSTED BY BODY EFFECT
A transistor device including a substrate, a gate structure, a first doped region, a second doped region and a body region is provided. The gate structure is...
2018/0061949 COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS
Implementations of the present disclosure relate to semiconductor devices such as transistors used for amplifying or switching electronic signals. In one...
2018/0061948 EPITAXIAL WAFER FOR HETERO-JUNCTION BIPOLAR TRANSISTOR AND HETERO-JUNCTION BIPOLAR TRANSISTOR
An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor capable of reducing the resistance of the sub-collector...
2018/0061947 High Voltage Vertical Semiconductor Device with Multiple Silicon Pillars in a Racetrack Arrangement
A semiconductor device including a dummy pillar and a plurality of racetrack pillars. The dummy pillar of semiconductor material extends in a first lateral...
2018/0061946 VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of...
2018/0061945 VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of...
2018/0061944 FORMING NANOSHEET TRANSISTORS WITH DIFFERING CHARACTERISTICS
A method of forming a transistor in an integrated circuit device can include forming a first and second nanosheet structure with alternating sheets of silicon...
2018/0061943 FIELD-EFFECT TRANSISTOR (FET) DEVICES EMPLOYING ADJACENT ASYMMETRIC ACTIVE GATE / DUMMY GATE WIDTH LAYOUT
Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is...
2018/0061942 STRUCTURE AND PROCESS TO TUCK FIN TIPS SELF-ALIGNED TO GATES
A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure...
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