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Patent # Description
2018/0069003 FABRICATION OF FIN FIELD EFFECT TRANSISTORS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICES INCLUDING...
A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate,...
2018/0069002 SILICON NITRIDE FILL FOR PC GAP REGIONS TO INCREASE CELL DENSITY
A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the...
2018/0069001 SEMICONDUCTOR DEVICE WITH INCREASED SOURCE/DRAIN AREA
A semiconductor device includes a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, and a spacer arranged...
2018/0069000 GATE CUT WITH INTEGRATED ETCH STOP LAYER
A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first...
2018/0068999 Leakage Current Suppression Methods and Related Structures
A method and structure for suppressing band-to-band tunneling current in a semiconductor device having a high-mobility channel material includes forming a...
2018/0068998 BIPOLAR JUNCTION TRANSISTOR
A bipolar junction transistor (BJT) includes a semiconductor substrate and a first isolation structure. The semiconductor substrate includes a first fin...
2018/0068997 CASCODE CIRCUIT AND AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A FIELD ELECTRODE
In an aspect, a cascode circuit can include a high-side transistor and a low-side transistor. The source of the high-side transistor can be coupled to the...
2018/0068995 OPTOELECTRONIC SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An optoelectronic semiconductor device and a manufacturing method are disclosed. The manufacturing method includes steps of: a step of providing a microsized...
2018/0068994 SELF-ALIGNED THREE DIMENSIONAL CHIP STACK AND METHOD FOR MAKING THE SAME
Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips...
2018/0068993 THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a...
2018/0068992 DISPLAY DEVICE
A display device including: a substrate including a display area and a non-display area; a first pad terminal and a second pad terminal disposed in the...
2018/0068991 LIGHT EMITTING DEVICE PACKAGE
A light emitting device package includes a cell array including a plurality of semiconductor light emitting units, and having a first surface and a second...
2018/0068990 OPTICAL COUPLING DEVICE, MANUFACTURING METHOD THEREOF, AND POWER CONVERSION SYSTEM
In order to improve properties, an optical coupling device has a potting resin and an internal mold resin between a light emitting element and a light...
2018/0068989 FORMING EMBEDDED CIRCUIT ELEMENTS IN SEMICONDUCTOR PACKAGE ASSEMBLES AND STRUCTURES FORMED THEREBY
Methods of forming stacked die assemblies are described. Those methods/structures may include forming a circuit element on a first substrate, wherein a first...
2018/0068988 DEVICE WITH MULTIPLE, STACKED LIGHT EMITTING DEVICES
A device according to embodiments of the invention includes a first semiconductor light emitting layer disposed between a first n-type region and a first...
2018/0068987 Display Apparatus and Methods
A display includes a plurality of pixel chips, chixels, provided on a substrate. The chixels and the light emitters thereon may be shaped, sized and arranged...
2018/0068986 LED MODULE AND METHOD FOR FABRICATING THE SAME
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding...
2018/0068985 Package-on-Package Structure and Method
A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor...
2018/0068984 METHOD FOR BONDING AND INTERCONNECTING INTEGRATED CIRCUIT DEVICES
A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are...
2018/0068983 ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME
An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit...
2018/0068982 METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY
A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in...
2018/0068981 SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips...
2018/0068980 MULTIPLE INTERCONNECTIONS BETWEEN DIE
Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a...
2018/0068979 Multi-Stack Package-on-Package Structures
Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first...
2018/0068978 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package structure includes a redistribution (RDL) layer, a first chip, at least one second chip, an encapsulant and a third chip. The...
2018/0068977 CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE
A packaging method and a packaging structure are provided. The method includes: providing a first substrate and a second substrate, the second substrate having...
2018/0068976 Semiconductor Device and Method of Forming Insulating Layers Around Semiconductor Die
A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the...
2018/0068975 Semiconductor Devices and Method for Forming Semiconductor Devices
A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor...
2018/0068974 ADVANCED CHIP TO WAFER STACKING
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first...
2018/0068973 ATOMIZATION MECHANISM FOR COOLING A BOND HEAD
An atomization mechanism for cooling a bond head comprises an atomization module and a conduit. In use, the atomization module receives gas and liquid from a...
2018/0068972 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end...
2018/0068971 SEMICONDUCTOR DEVICE
Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main...
2018/0068970 SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER
A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional...
2018/0068969 VARIABLE BALL HEIGHT ON BALL GRID ARRAY PACKAGES BY SOLDER PASTE TRANSFER
BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold...
2018/0068968 Post-Passivation Interconnect Structure and Methods Thereof
A method includes providing a die including a substrate and a bonding pad over the substrate, forming a connective layer over the die, and forming the landing...
2018/0068967 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD
A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a...
2018/0068966 SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS
A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically...
2018/0068965 Conductive Pad Structure for Hybrid Bonding and Methods of Forming Same
A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the...
2018/0068964 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a...
2018/0068963 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate...
2018/0068962 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a...
2018/0068961 PROTECTION CIRCUIT AND INTEGRATED CIRCUIT
Protection circuit and integrated circuit are provided. A protection circuit includes a discharge passage, configured to perform an electro-static discharge...
2018/0068960 METHOD OF MAKING PACKAGE ASSEMBLY INCLUDING STRESS RELIEF STRUCTURES
A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is...
2018/0068959 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE
A semiconductor package is provided, which includes: a circuit structure having a first bottom surface and a first top surface opposite to the first bottom...
2018/0068958 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first substrate, and a first semiconductor...
2018/0068957 SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR
Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a...
2018/0068956 SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME
A semiconductor package and a method of fabricating the same, the method including mounting semiconductor chips on a substrate; forming a mold layer that...
2018/0068955 SECURE CHIPS WITH SERIAL NUMBERS
An electronic device comprising a semiconductor chip which comprises a plurality of structures formed in the semiconductor chip, wherein the semiconductor chip...
2018/0068954 ENHANCING BARRIER IN AIR GAP TECHNOLOGY
A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are...
2018/0068953 ENHANCING BARRIER IN AIR GAP TECHNOLOGY
A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are...
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