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Patent # Description
2018/0068952 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first...
2018/0068951 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer...
2018/0068950 LOW RESISTANCE CONTACTS INCLUDING INTERMETALLIC ALLOY OF NICKEL, PLATINUM, TITANIUM, ALUMINUM AND TYPE IV...
A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti)...
2018/0068949 THROUGH VIA STRUCTURE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A through via structure includes a semiconductor substrate, an underlying insulation layer, a conductive via and a sidewall insulation layer. The underlying...
2018/0068948 ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES
Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a...
2018/0068947 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer comprising an upper surface and a recess through the upper surface and including a lower part, an upper...
2018/0068946 ISOLATION DEVICE
An isolation system, isolation device, and Integrated Circuit are disclosed. The isolation system is described to include an integrated circuit chip having a...
2018/0068945 MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT
A semiconductor package, e.g., wafer, chip, interposer, etc., includes a multi terminal capacitor within an input output (IO) path. The multi terminal...
2018/0068944 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width...
2018/0068943 METAL VIA STRUCTURE
A fabrication process including the following steps for making a metal via structure is disclosed. A substrate with at least a metal pad configured thereon is...
2018/0068942 ELECTRONIC DEVICE
This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at...
2018/0068941 Copper Interconnect For Improving Radio Frequency (RF) Silicon-On-Insulator (SOI) Switch Field Effect...
A radio frequency (RF) switch includes a plurality of silicon-on-insulator (SOI) CMOS transistors. A first metal layer (M1) includes traces that connect the...
2018/0068940 DISPLAY DEVICE HAVING CONNECTION UNIT
A display device includes a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line...
2018/0068939 REDISTRIBUTION LAYER LINES
Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a...
2018/0068938 SCALABLE SEMICONDUCTOR INTERPOSER INTEGRATION
An electronic package including a first substrate, a second substrate, a first standoff substrate, and a second standoff substrate. A clearance is formed...
2018/0068937 Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An...
2018/0068936 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a...
2018/0068935 VERTICAL AND HORIZONTAL CIRCUIT ASSEMBLIES
In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality...
2018/0068934 PACKAGE FOR DIE-BRIDGE CAPACITOR
In some examples, a device comprises a first leadframe segment, a second leadframe segment, and a first transistor, wherein the first transistor is...
2018/0068933 LEAD FRAME AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Disclosed are a lead frame for a semiconductor package, comprising: an anode 10, a cathode 20, a molding part 30, terminal parts 90 and 91, wherein one or more...
2018/0068932 LEADFRAME PACKAGE WITH STABLE EXTENDED LEADS
Embodiments of the present disclosure are directed to leadframes having the cantilevered extension that includes an integral support on the end of the lead...
2018/0068931 SEMICONDUCTOR CHIP, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF CONNECTING THE SEMICONDUCTOR CHIP TO...
A semiconductor chip includes: a base substrate; a conductive pad on one surface of the base substrate; an insulating layer on the one surface of the base...
2018/0068930 SSI PoP
An assembly can include a first microelectronic package and a circuit structure comprising a plurality of dielectric layers and electrically conductive...
2018/0068929 NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY
A first photoresist layer is patterned with a first pattern that includes an opening in a region between areas of two adjacent via holes to be formed. The...
2018/0068928 SEMICONDUCTOR DEVICE
A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second...
2018/0068927 DISTRIBUTION AND STABILIZATION OF FLUID FLOW FOR INTERLAYER CHIP COOLING
A method of forming metallic pillars between a fluid inlet and outlet for two-phase fluid cooling. The method may include; forming an arrangement of metallic...
2018/0068926 ENERGY STORAGE MATERIAL FOR THERMAL MANAGEMENT AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS
Embodiments of the present disclosure describe an energy storage material for thermal management and associated techniques and configurations. In one...
2018/0068925 ON-CHIP INTEGRATED TEMPERATURE PROTECTION DEVICE BASED ON GEL ELECTROLYTE
A field effect transistor includes an exposed channel region disposed between a source region and a drain region. A gate electrode is disposed over the exposed...
2018/0068924 SYSTEMS FOR THERMAL MANAGEMENT AND METHODS FOR THE USE THEREOF
In accordance with the present invention, there are provided heat dispersing articles, assemblies containing same, methods for the preparation thereof, and...
2018/0068923 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE
A disclosed semiconductor device includes a buffer layer formed of a compound semiconductor on a substrate, a first semiconductor layer formed of a compound...
2018/0068922 INTEGRATED CIRCUIT DIE AND MANUFACTURE METHOD THEREOF
The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the...
2018/0068921 Methods and Apparatus for Self-Alignment of Integrated Circuit Dies
The present disclosure describes apparatuses and techniques for self-aligning integrated circuit (IC) dies. In some aspects, a hydrophobic material is...
2018/0068920 WAFER LEVEL SEMICONDUCTOR DEVICE WITH WETTABLE FLANKS
A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom...
2018/0068919 DISPLAY APPARATUS
Provided is a display apparatus capable of minimizing defect occurrences during manufacturing of the display apparatus while securing a long lifespan of the...
2018/0068918 POWER MODULE
A power module will be provided which can suppress insulation performance deterioration caused by heat cycle to ensure insulation performance, by suppressing...
2018/0068917 LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE
In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or...
2018/0068916 LID ATTACH OPTIMIZATION TO LIMIT ELECTRONIC PACKAGE WARPAGE
An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band...
2018/0068915 ELECTRONIC ELEMENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an...
2018/0068914 PACKAGING STRUCTURE AND METHOD OF INTEGRATED SENSOR
Provided are an encapsulation structure and encapsulation method for an integrated sensor. The encapsulation structure comprises: a first substrate (1) and a...
2018/0068913 SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device having a structure in which a resin hardly enters between an insert electrode and a nut...
2018/0068912 PACKAGE BASE CORE AND SENSOR PACKAGE STRUCTURE
The present disclosure provides a package base core and a sensor package structure. The package base core includes a substrate and at least one stopper, or the...
2018/0068911 BOARD FOR ELECTRONIC COMPONENT PACKAGE, ELECTRONIC COMPONENT PACKAGE, AND METHOD OF MANUFACTURING BOARD FOR...
A board for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating...
2018/0068910 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the...
2018/0068909 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
A plasma processing apparatus including a processing chamber, a radio frequency power source, a monitoring unit, and a calculation unit is provided. In the...
2018/0068908 SMART IN SITU CHAMBER CLEAN
A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean...
2018/0068907 INTEGRATED CIRCUIT DESIGNING SYSTEM AND A METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT
A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering...
2018/0068906 ANOMALY DETECTION METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS
A method performed by a semiconductor manufacturing apparatus includes calculating, by a processor of the semiconductor manufacturing apparatus, 3 standard...
2018/0068904 LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A...
2018/0068903 LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A...
2018/0068902 METHOD TO CO-INTEGRATE SiGe AND Si CHANNELS FOR FINFET DEVICES
A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in...
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