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| Patent # | Description |
|---|---|
| 2018/0068750 |
MOLTEN FUEL NUCLEAR REACTOR WITH NEUTRON REFLECTING COOLANT Configurations of molten fuel salt reactors are described that utilize neutron-reflecting coolants or a combination of primary salt coolants and secondary... |
| 2018/0068749 |
CONTROL ROD DRIVE MECHANISM (CRDM) MOUNTING SYSTEM FOR PRESSURIZED WATER
REACTORS A standoff supporting a control rod drive mechanism (CRDM) in a nuclear reactor is connected to a distribution plate which provides electrical power and... |
| 2018/0068748 |
Magnetic Field Plasma Confinement for Compact Fusion Power In one embodiment, a fusion reactor includes two internal magnetic coils suspended within an enclosure, a center magnetic coil coaxial with the two internal... |
| 2018/0068747 |
System for Supporting Structures Immersed in Plasma A fusion reactor includes an enclosure having a first end, a second end opposite the first end, and a midpoint substantially equidistant between the first and... |
| 2018/0068745 |
SYSTEMS FOR NUCLEAR FUSION HAVING A FIXED MOUNTING ASSEMBLY FOR A SECOND
REACTANT Methods, apparatuses, devices, and systems for creating, controlling, conducting, and optimizing fusion activities of nuclei. The controlled fusion activities... |
| 2018/0068744 |
METHOD OF ACHIEVING CONTROLLED NUCLEAR FUSION IN A CHAMBER Methods, apparatuses, devices, and systems for creating, controlling, conducting, and optimizing fusion activities of nuclei. The controlled fusion activities... |
| 2018/0068743 |
TEST METHODS OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS USED
THEREIN A semiconductor system includes a medium controller and a semiconductor module. The medium controller outputs an address that is sequentially counted in a test... |
| 2018/0068742 |
DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING
THE DEVICE Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device... |
| 2018/0068741 |
TRACKING ADDRESS RANGES FOR COMPUTER MEMORY ERRORS Tracking address ranges for computer memory errors including detecting, by memory logic, an error at a memory address, the memory address representing one or... |
| 2018/0068740 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory... |
| 2018/0068739 |
MEMORY DEVICE According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a... |
| 2018/0068738 |
SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier electrically connected to the bit... |
| 2018/0068737 |
ERASING MEMORY SEGMENTS IN A MEMORY BLOCK OF MEMORY CELLS USING SELECT
GATE CONTROL LINE VOLTAGES A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device... |
| 2018/0068736 |
MEMORY SYSTEM AND METHOD FOR OPERATING THE MEMORY SYSTEM A memory system includes: a memory device; and a controller that is functionally coupled to the memory device, wherein the controller sets a first read bias... |
| 2018/0068735 |
Method to Reduce Program Disturbs in Non-Volatile Memory Cells A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the... |
| 2018/0068734 |
METHODS FOR READ RETRIES AND APPARATUSES USING THE SAME The invention introduces a method for read retries, performed by a processing unit, including at least the following steps: in boot time, generating and... |
| 2018/0068733 |
SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF A semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory... |
| 2018/0068732 |
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second... |
| 2018/0068731 |
MEMORY SYSTEM AND OPERATING METHOD THEREOF A memory system may include: a memory device including a plurality of memory blocks; and a controller suitable for managing the memory blocks as a plurality of... |
| 2018/0068730 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a plurality of memory layers stacked on... |
| 2018/0068729 |
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based... |
| 2018/0068728 |
NONVOLATILE MEMORY DEVICE A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to... |
| 2018/0068727 |
SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a plurality of memory cells, and a control circuit configured perform a multi-bit write operation on the memory cells in... |
| 2018/0068726 |
ERROR MITIGATION FOR 3D NAND FLASH MEMORY NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a... |
| 2018/0068725 |
WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally... |
| 2018/0068724 |
Memory Cells, Memory Cell Programming Methods, Memory Cell Reading
Methods, Memory Cell Operating Methods, and... Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In... |
| 2018/0068723 |
OXIDE BASED MEMORY Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory... |
| 2018/0068722 |
RESISTIVE MEMORY ACCELERATOR Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array... |
| 2018/0068721 |
Memory with Margin Current Addition and Related Methods In accordance with an embodiment, a memory includes: a memory element, a sense amplifier circuit configured to sense a difference during a sense operation... |
| 2018/0068720 |
CELL PROGRAMMING VERIFICATION Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase... |
| 2018/0068719 |
MEMORY SYSTEM According to one embodiment, a controller writes first processed data acquired by a first process into a nonvolatile memory during a first period. The... |
| 2018/0068718 |
SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor... |
| 2018/0068717 |
TUNABLE NEGATIVE BITLINE WRITE ASSIST AND BOOST ATTENUATION CIRCUIT An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes... |
| 2018/0068716 |
SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor... |
| 2018/0068715 |
SEMICONDUCTOR MEMORY DEVICE HAVING BIT CELLS A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second... |
| 2018/0068714 |
LOWER POWER HIGH SPEED DECODING BASED DYNAMIC TRACKING FOR MEMORIES A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert... |
| 2018/0068713 |
Array Power Supply-Based Screening of Static Random Access Memory Cells
for Bias Temperature Instability A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory... |
| 2018/0068712 |
SEMICONDUCTOR DEVICE A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in... |
| 2018/0068711 |
OVERVOLTAGE PROTECTION FOR A FINE GRAINED NEGATIVE WORDLINE SCHEME A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell... |
| 2018/0068710 |
SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a... |
| 2018/0068709 |
SEMICONDUCTOR MEMORY DEVICE A semiconductor memory device includes a cell array including memory cells. A potential generation circuit applies a first potential to the memory cells. A... |
| 2018/0068708 |
SEMICONDUCTOR DEVICE A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being... |
| 2018/0068707 |
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME A semiconductor memory device includes a substrate, a ground selection line, a word line, an insulating layer, a vertical channel portion, and a first... |
| 2018/0068706 |
SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array to which a... |
| 2018/0068705 |
REDUNDANCY ARRAY COLUMN DECODER FOR MEMORY Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other... |
| 2018/0068704 |
MEMORY DEVICE A memory device includes: a memory cell; a data buffer which receives write data; a first latch circuit which latches data stored in the memory cell; a second... |
| 2018/0068703 |
MAGNONIC HOLOGRAPHIC MEMORY AND METHODS An electronic device using an array of magnetic wave guides is shown. In one example a memory device is shown that utilizes spin waves and a magnet storage... |
| 2018/0068702 |
MAGNETIC MEMORY DEVICES HAVING MEMORY CELLS AND REFERENCE CELLS WITH
DIFFERENT CONFIGURATIONS A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a... |
| 2018/0068701 |
Devices, systems, and methods for increasing the usable life of a storage
system by optimizing the energy of... In certain aspects, a device may include a memory and a controller coupled to the memory. The controller may be configured to process data to form codewords... |
| 2018/0068700 |
MEMORY ARCHITECTURE WITH MULTI-BANK MEMORY CELL ARRAY ACCESSED BY LOCAL
DRIVE CIRCUIT WITHIN MEMORY BANK A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of... |
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