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Patent # Description
2018/0076329 GATE-ALL-AROUND FIN DEVICE
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a...
2018/0076328 GATE-ALL-AROUND FIN DEVICE
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a...
2018/0076327 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes: a gate structure extending along a first direction on a substrate, in which the gate structure includes a first edge and a...
2018/0076326 FINFET WITH REDUCED SERIES TOTAL RESISTANCE
Selective epitaxial growth is used to form a hetero-structured source/drain region to fill an etched recess in a silicon fin for an n-type FinFET device.
2018/0076325 METAL OXIDE SEMICONDUCTOR HAVING EPITAXIAL SOURCE DRAIN REGIONS AND A METHOD OF MANUFACTURING SAME USING DUMMY...
A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
2018/0076324 METHOD OF CONTACT FORMATION BETWEEN METAL AND SEMICONDUCTOR
Implementations of the present disclosure generally relate to improved semiconductor devices and methods of manufacture thereof. More specifically,...
2018/0076323 METHOD FOR OPERATION OF A FIELD EFFECT TRANSISTOR ARRANGEMENT
A method is provided for operation a field effect transistor arrangement, the field effect transistor arrangement having a planar channel layer including a...
2018/0076322 SEMICONDUCTOR STRUCTURE AND ASSOCIATED FABRICATING METHOD
A semiconductor structure is disclosed. The semiconductor structure includes: a substrate of a first conductivity; a first region of the first conductivity...
2018/0076321 Metallization Layers for Semiconductor Devices and Methods of Forming Thereof
A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to...
2018/0076320 POWER MOSFET WITH METAL FILLED DEEP SOURCE CONTACT
A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells)...
2018/0076319 CLOSED CELL LATERAL MOSFET USING SILICIDE SOURCE AND METHOD OF FORMING
A closed cell lateral MOSFET device includes minimally sized source/body contacts formed in source cells with silicided source and body diffusion regions...
2018/0076318 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
According to an embodiment, semiconductor device 1 includes: a drift layer 12 of a first conductivity type; a base layer 13 of a second conductivity type; a...
2018/0076317 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the...
2018/0076316 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A MOS gate having a trench gate structure is formed on the front surface side of a silicon carbide substrate. A gate trench of the trench gate structure goes...
2018/0076315 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A SJ-MOSFET includes a parallel pn layer in which an n-type drift region and a p-type partition region are alternately arranged repeatedly along a direction...
2018/0076314 METHOD FOR FABRICATING FINFET WITH P/N STACKED FINS
A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of...
2018/0076313 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column...
2018/0076312 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a...
2018/0076311 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor...
2018/0076310 ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH
A high electron mobility transistor (HEMT)gallium nitride (GaN) bidirectional blocking device includes a hetero-j unction structure comprises a first...
2018/0076309 POWER SEMICONDUCTOR DEVICE WITH DV/DT CONTROLLABILITY
A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body coupled to a first load terminal and a second load...
2018/0076308 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source...
2018/0076307 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third...
2018/0076306 DUAL WIDTH FINFET
A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET...
2018/0076305 SELECTIVELY FORMED GATE SIDEWALL SPACER
A method for forming a semiconductor device comprises forming a fin on a substrate and forming a sacrificial gate over a channel region of the fin. A hydrogen...
2018/0076304 PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET
In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into...
2018/0076303 PARASITIC CAPACITANCE REDUCING CONTACT STRUCTURE IN A FINFET
In a fin-Field Effect Transistor (finFET), a recess is created at a location of a fin, the fin being coupled to a gate of the finFET, the recess extending into...
2018/0076302 SPACER FORMATION ON SEMICONDUCTOR DEVICE
A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel...
2018/0076301 EMBEDDED ENDPOINT FIN REVEAL
A semiconductor structure is provided. The semiconductor structure includes a plurality of fins formed from a substrate, at least one liner segment formed...
2018/0076299 EPITAXIAL AND SILICIDE LAYER FORMATION AT TOP AND BOTTOM SURFACES OF SEMICONDUCTOR FINS
A method of making a semiconductor device includes forming a fin in a substrate; depositing a first spacer material to form a first spacer around the fin;...
2018/0076298 COVER MEMBER FOR A ROBOT USED IN A PAINTING PROCESS HAVING ABSORPTIVE PROPERTIES
A cover member for a robot used in a painting process includes an inner knitted substructure, an outer knitted substructure and a spacer yarn positioned...
2018/0076297 TRENCH POWER SEMINCONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A trench power semiconductor device and a manufacturing method thereof are provided. The trench power semiconductor device includes a substrate, an epitaxial...
2018/0076296 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device having stable electrical characteristics is provided. A semiconductor device that can be miniaturized or highly integrated is provided....
2018/0076295 HEAT MANAGEMENT IN A MULTI-FINGER FET
The present disclosure addresses thermal issues in a multi gate finger field-effect transistor (FET) by providing a multi-gate finger FET arrangement where the...
2018/0076294 SEMICONDUCTOR DEVICE AND METHOD FOR MANURACTURING THE SAME
A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first...
2018/0076293 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The...
2018/0076292 OXIDE SEMICONDUCTOR, SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE, AND SOLID-STATE IMAGING DEVICE
According to one embodiment, an oxide semiconductor includes indium (In), gallium (Ga), and silicon (Si). A composition ratio of Si to In (Si/In) in the oxide...
2018/0076291 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a first element portion. The first element portion includes first and second semiconductor layers,...
2018/0076290 SILICON CARBIDE SEMICONDUCTOR DEVICE
An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does...
2018/0076289 SWITCHING DEVICE AND METHOD OF MANUFACTURING THE SAME
A switching device includes a semiconductor substrate; first and second trenches; gate insulating layers; and gate electrodes. The semiconductor substrate...
2018/0076288 TRENCH ISOLATION STRUCTURES AND METHODS FOR FORMING THE SAME
A trench isolation structure is provided. The trench isolation structure includes a substrate. A polygonal trench is disposed in the substrate. An insulating...
2018/0076287 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE
A semiconductor device includes: a nitride semiconductor layer; a silicon substrate including a first region of a first conductivity type, a second region of a...
2018/0076286 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed...
2018/0076285 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A drift layer of a first conductivity type is made of silicon carbide. A body region of a second conductivity type is provided on the drift layer. A source...
2018/0076284 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE
A semiconductor device may include the following elements: a first doped portion; a second doped portion; an enclosing member, which encloses both the first...
2018/0076283 HIGH PERFORMANCE SUPER-BETA NPN (SBNPN)
A method for making a super .beta. NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a...
2018/0076282 SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
A semiconductor device and a method for forming the same are provided. The method includes forming a patterned mask on a substrate, wherein the patterned mask...
2018/0076281 DEEP CHANNEL ISOLATED DRAIN METAL-OXIDE-SEMICONDUCTOR TRANSISTORS
Isolated drain MOS transistors provide solutions to overcome the short channel effects of Metal-Oxide-Semiconductor (MOS) transistors. Instead of reducing...
2018/0076280 SHALLOW DRAIN METAL-OXIDE-SEMICONDUCTOR TRANSISTORS
Shallow drain MOS transistors provide solutions to overcome the short channel effects of Metal-Oxide-Semiconductor (MOS) transistors. Instead of reducing...
2018/0076279 POWERMOS
A process of manufacturing a device is disclosed. The process includes forming an epitaxial layer of a first conductivity type on in a substrate, forming a...
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