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Patent # Description
2018/0076177 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor package structure includes: (a) disposing at least one semiconductor element on a conductive structure, wherein the...
2018/0076176 SIGNAL ISOLATOR HAVING BIDIRECTIONAL COMMUNICATION BETWEEN DIE
Methods and apparatus for bi-directional communication between first and second die of a signal isolator for feedback and/or diagnostic signals. In...
2018/0076175 Redistribution Layers in Semiconductor Packages and Methods of Forming Same
An embodiment package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and a conductive line electrically...
2018/0076174 SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed...
2018/0076173 SEMICONDUCTOR DEVICE INCLUDING TWO OR MORE CHIPS MOUNTED OVER WIRING SUBSTRATE
A semiconductor device includes a composite chip mounted over the a wiring substrate, the composite chip including a first area, a second area that is provided...
2018/0076172 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic...
2018/0076171 MICROELECTRONIC INTERPOSER FOR A MICROELECTRONIC PACKAGE
A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in...
2018/0076170 ADVANCED CHIP TO WAFER STACKING
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first...
2018/0076169 CHIP BONDING PROCESS
A chip bonding process is provided, including following steps of: providing a plurality of microchips, providing a substrate, applying a flux which is pasty, a...
2018/0076168 Fluidic Self Assembly of Contact Materials
Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for forming contacts during fluidic assembly.
2018/0076167 METALLIC RIBBON FOR POWER MODULE PACKAGING
A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic...
2018/0076166 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor is disclosed. A carrier substrate is provided. A redistribution layer (RDL) structure is formed on the carrier...
2018/0076165 METHOD OF FORMING SOLDER BUMPS
A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on...
2018/0076164 METHOD OF FORMING SOLDER BUMPS
A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on...
2018/0076163 METHOD OF FORMING SOLDER BUMPS
A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on...
2018/0076162 CHIP MOUNTING STRUCTURE
Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so...
2018/0076161 NICKEL-TIN MICROBUMP STRUCTURES AND METHOD OF MAKING SAME
Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment,...
2018/0076160 MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER
A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is...
2018/0076159 Pad Design for Reliability Enhancement in Packages
A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding...
2018/0076158 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality...
2018/0076157 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at...
2018/0076156 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip...
2018/0076155 Extremely High Frequency Electronic Component
A circuit substrate of an extremely high frequency electronic component having an organic substrate material and at least one hollow space incorporated into...
2018/0076154 SINGLE LEAD-FRAME STACKED DIE GALVANIC ISOLATOR
Isolators for providing electrical isolation between two circuits operating at different voltages are described, in which multiple semiconductor dies including...
2018/0076153 POWER MODULE ASSEMBLY WITH REDUCED INDUCTANCE
A power module assembly has a plurality of electrically conducting layers, including a first layer and a third layer. One or more electrically insulating...
2018/0076152 High-voltage Light Emitting Diode and Fabrication Method Thereof
A fabrication method of a high-voltage light-emitting diode includes the steps of providing a substrate, and forming a light-emitting epitaxial laminated layer...
2018/0076151 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive...
2018/0076150 SEMICONDUCTOR CHIP, SEMICONDUCTOR APPARATUS, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER DICING METHOD
Provided are a semiconductor chip, a semiconductor apparatus, a semiconductor wafer, and a semiconductor wafer dicing method in which chipping is prevented...
2018/0076149 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device including a stacked assembly. The stacked assembly includes a metal substrate, a stacked substrate mounted on the metal substrate and...
2018/0076148 THROUGH-MOLD FEATURES FOR SHIELDING APPLICATIONS
Through-mold features for shielding applications. In some embodiments, a packaged module can include a packaging substrate having a ground plane, and one or...
2018/0076147 SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE MODULE
A semiconductor package includes a frame including a through-hole, an electronic component disposed in the through-hole, a redistribution portion disposed...
2018/0076146 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a semiconductor device includes a substrate, and a first shield member provided on or in the substrate. The device further includes a...
2018/0076145 SELF-ALIGNED TRANSISTORS FOR DUAL-SIDE PROCESSING
An integrated circuit structure may include an alignment column on a front-side surface of an isolation layer. The alignment column may extend through a...
2018/0076144 Contact Structure and Method of Forming
Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an...
2018/0076143 METAL ALLOY CAPPING LAYERS FOR METALLIC INTERCONNECT STRUCTURES
A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the...
2018/0076142 Double-Sided Semiconductor Package and Dual-Mold Method of Making Same
A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to...
2018/0076141 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric...
2018/0076140 SEMICONDUCTOR DEVICES HAVING INTERCONNECTION STRUCTURE
Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact...
2018/0076139 CONTACT FOR SEMICONDUCTOR DEVICE
A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second...
2018/0076138 SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS
A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different...
2018/0076137 UTILIZATION OF BACKSIDE SILICIDATION TO FORM DUAL SIDE CONTACTED CAPACITOR
An integrated circuit structure may include a capacitor having a semiconductor layer as a first plate and a gate layer as a second plate. A capacitor...
2018/0076136 TRIMMING DEVICE
In a trimming device, a counter circuit generates n-bit setting data for n-bit trimming data used to trim the trimmed circuit. A trimming data generation...
2018/0076135 Inductor System and Method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors....
2018/0076134 INTEGRATED CIRCUIT WITH SHIELDING STRUCTURES
A semiconductor device includes an interconnect structure disposed over a semiconductor substrate. The interconnect structure includes a first device disposed...
2018/0076133 INTERCONNECT SCALING
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the...
2018/0076132 Self-Aligned Interconnection Structure and Method
The present disclosure provides a method that includes providing a substrate having a first dielectric material layer and first conductive features that are...
2018/0076131 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor...
2018/0076130 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and an interconnect portion....
2018/0076129 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a...
2018/0076128 INTEGRATED CIRCUITS INCLUDING A DUMMY METAL FEATURE AND METHODS OF FORMING THE SAME
Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an...
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