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Patent # Description
2018/0076127 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable...
2018/0076126 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Disclosed herein is a semiconductor device including: a substrate having a first conductive layer and a second conductive layer arranged deeper than the first...
2018/0076124 ELECTRICAL CONNECTIVITY OF DIE TO A HOST SUBSTRATE
According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor....
2018/0076123 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING REDISTRIBUTION PATTERN
A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a...
2018/0076122 INTERPOSER, SEMICONDUCTOR PACKAGE STRUCTURE, AND SEMICONDUCTOR PROCESS
A semiconductor process includes: (a) attaching a metal layer on a carrier; (b) removing a portion of the metal layer to form a through hole and at least one...
2018/0076121 CHIP PACKAGE AND PACKAGE SUBSTRATE
A package substrate is provided. The package substrate includes a dielectric layer and a passive component embedded in the dielectric layer and contacting the...
2018/0076120 SEMICONDUCTOR DEVICE AND METHOD OF ALIGNING SEMICONDUCTOR WAFERS FOR BONDING
A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one...
2018/0076119 TIN-ZINC MICROBUMP STRUCTURES AND METHOD OF MAKING SAME
Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment,...
2018/0076118 SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package includes a copper lead frame, a copper oxide compound layer and an encapsulant. The copper oxide compound layer is in contact...
2018/0076117 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a metal plate having an upper surface (first...
2018/0076116 Spot-Solderable Leads for Semiconductor Device Packages
A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has...
2018/0076115 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip...
2018/0076114 HEAT PIPE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed...
2018/0076113 CHIP PACKAGE FOR TWO-PHASE COOLING AND ASSEMBLY PROCESS THEREOF
Devices that have integrated cooling structures for two-phase cooling and methods of assembly thereof are provided. In one example, a chip manifold can be...
2018/0076112 Flexible System Integration to Improve Thermal Properties
In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor...
2018/0076111 VARIABLE PIN FIN CONSTRUCTION TO FACILITATE COMPLIANT COLD PLATES
A device can comprise a plurality of layers stacked and bonded on one another, wherein at least one layer of the plurality of layers comprises: a first active...
2018/0076110 BACKSIDE SPACER STRUCTURES FOR IMPROVED THERMAL PERFORMANCE
Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are...
2018/0076109 INTERCONNECT ARRANGEMENT WITH STRESS-REDUCING STRUCTURE AND METHOD OF FABRICATING THE SAME
A semiconductor device structure and a method of fabricating the same are provided. The method for manufacturing a semiconductor structure includes forming a...
2018/0076108 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes forming a preliminary package, on a supporting substrate, which includes a connection substrate, a...
2018/0076107 SEMICONDUCTOR PACKAGE
A semiconductor package comprises a resin material, a semiconductor chip in the resin material, and a metal member in the resin material. The metal member has...
2018/0076106 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME
The present invention provides a semiconductor device and a method of making the same for suppressing warpages of an article due to a difference of temperature...
2018/0076105 PACKAGE SUBSTRATE FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING THE SAME AND METHOD OF...
A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top...
2018/0076104 SEMICONDUCTOR DEVICE
A semiconductor device includes: an insulating board; a circuit pattern disposed on the insulating board; a semiconductor chip connected to the circuit...
2018/0076103 FAN OUT WAFER LEVEL PACKAGE TYPE SEMICONDUCTOR PACKAGE AND PACKAGE ON PACKAGE TYPE SEMICONDUCTOR PACKAGE...
A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base...
2018/0076102 DISPLAY DEVICE INCLUDING A TEST UNIT
A display device includes a pixel connected to a data line, a data pad connected to the data line, and a first test area. The first test area includes a test...
2018/0076101 TEST CELL FOR LAMINATE AND METHOD
A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at...
2018/0076100 Systems and Methods for Detection of Plasma Instability by Electrical Measurement
A wafer is positioned on a wafer support apparatus beneath an electrode such that a plasma generation region exists between the wafer and the electrode....
2018/0076099 METHOD AND MACHINE FOR EXAMINING WAFERS
Method and machine utilizes the real-time recipe to perform weak point inspection on a series of wafers during the fabrication of integrated circuits. Each...
2018/0076098 APPARATUS AND METHOD FOR REDUCING WAFER WARPAGE
An apparatus and a method for reducing wafer warpage are provided. The method includes positioning a mold wafer structure on a stage. The mold wafer structure...
2018/0076097 Nonplanar Device and Strain-Generating Channel Dielectric
Various methods are disclosed herein for fabricating non-planar circuit devices having strain-producing features. An exemplary method includes forming a fin...
2018/0076096 CMOS DEVICE WITH DECREASED LEAKAGE CURRENT AND METHOD MAKING SAME
A method for making a CMOS device includes: providing a substrate with a semiconductor layer and a photoresist layer; irradiating the photoresist layer through...
2018/0076095 FORMING A HYBRID CHANNEL NANOSHEET SEMICONDUCTOR STRUCTURE
A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner...
2018/0076094 FINFET DEVICES
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
2018/0076093 VERTICAL TRANSISTORS HAVING DIFFERENT GATE LENGTHS
A method of forming a semiconductor device and resulting structures having vertical transistors with different gate lengths are provided. A sacrificial gate is...
2018/0076092 Selective Fin Cut
The present disclosure relates to methods and structures that involve the use of directed self-assembly to selectively remove at least one fin or fin section...
2018/0076091 FINFET GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a n-type gate structure over a first semiconductor fin, in which the n-type gate structure is fluorine incorporated and...
2018/0076090 METHODS FOR PRODUCING SEMICONDUCTOR DEVICES
A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first...
2018/0076089 APPARATUS FOR CUTTING SUBSTRATE AND SYSTEM FOR PROCESSING SAME
An apparatus for cutting a substrate is disclosed. The apparatus includes a main body containing a reactive solution and the substrate; and a catalytic cutting...
2018/0076088 METHOD OF PROCESSING WAFER
A method of processing a wafer includes forming a mask on portions of a face side of the wafer which correspond to devices; performing plasma etching on the...
2018/0076087 FILM FORMING METHOD AND FILM FORMING SYSTEM
In a film forming method for forming a cobalt film on a target substrate having a recess formed in a surface thereof to fill the recess with the cobalt film,...
2018/0076086 PROTECTIVE LINER BETWEEN A GATE DIELECTRIC AND A GATE CONTACT
A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate...
2018/0076085 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the...
2018/0076084 SEMICONDUTOR DEVICE INCLUDING STRAINED GERMANIUM AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes: forming a sacrificial layer on a first substrate, the sacrificial layer being made of a material...
2018/0076083 FOOTING REMOVAL FOR NITRIDE SPACER
Processing methods may be performed to remove unwanted materials from a substrate, such as an oxide footing. The methods may include forming an inert plasma...
2018/0076082 FORMING AIR GAP
A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a...
2018/0076081 Method of Planarizating Film
A method includes forming a patterned layer on a substrate having a first region and a second region being adjacent each other. The patterned layer includes...
2018/0076080 ELECTROSTATIC CHUCK AND SEMICONDUCTOR MANUFACTURING APPARATUS
An electrostatic chuck includes a first electrode provided in a first plane, a second electrode provided in a second plane parallel to the first plane, and an...
2018/0076079 Article Storage Facility
A wall member that covers lateral sides of an article storage rack includes a main wall portion that is installed in an orientation in which it extends along a...
2018/0076078 Container Storage Facility
A facility comprises an inactive gas supplying device configured to supply inert gas to a container, a transport device configured to carry a container into,...
2018/0076077 Article Storage Facility
A transport space Si is formed in front of an article storage rack 1, and a plurality of up-down partition bodies that partition storage sections 1a adjacent...
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