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Patent # Description
2018/0083033 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and...
2018/0083032 SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SEMICONDUTOR FILMS IN FIRST AND SECOND COLUMNAR BODIES
A semiconductor memory device according to an embodiment comprises: conductive layers stacked in a vertical direction on a semiconductor substrate; and first...
2018/0083031 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode...
2018/0083030 MEMORY DEVICES
A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of...
2018/0083029 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending...
2018/0083028 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a...
2018/0083027 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device includes a conductive layer; a first electrode layer provided above the conductive layer; a second electrode layer provided...
2018/0083026 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND CONTROLLING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a semiconductor layer, first electrodes, data storage regions, first conductive regions, contacts and second...
2018/0083025 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a gate insulating film on a semiconductor substrate, a memory cell array in a memory cell region, a first transistor in...
2018/0083024 Method of ONO Stack Formation
A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently...
2018/0083023 SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY MANUFACTURING METHOD
The present disclosure provides a semiconductor memory including a first capacitor, a second capacitor, and a transistor. The first capacitor includes a first...
2018/0083022 STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first...
2018/0083021 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device includes a stacked body 100, first insulating layers 45, a second insulating layer 46 and columnar portions CL. The stacked body 100...
2018/0083020 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes first wires extending in a first direction; second wires provided in a first interconnect layer including the first...
2018/0083019 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral...
2018/0083018 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a semiconductor substrate, a stepped structure including a stepped part in which a plurality of first insulating layers...
2018/0083017 THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate,...
2018/0083016 THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate,...
2018/0083015 THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate,...
2018/0083014 NON-VOLATILE SRAM MEMORY CELL AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
A non-volatile SRAM memory cell and a non-volatile semiconductor memory device capable of programming SRAM data in a SRAM to a non-volatile memory unit through...
2018/0083013 THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate,...
2018/0083012 ELECTRIC FUSE STRUCTURE
An electric fuse structure is disclosed. The electric fuse preferably includes a substrate and a stacked capacitor on the substrate. Preferably, the stacked...
2018/0083011 SEMICONDUCTOR DEVICES, MEMORY DIES AND RELATED METHODS
A semiconductor substrate is provided. Active areas and trench isolation regions are formed. The active areas extend along a first direction. Buried word lines...
2018/0083010 Method of Forming Semiconductor Device Including Tungsten Layer
A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over...
2018/0083009 METAL TRENCH CAPACITOR AND IMPROVED ISOLATION AND METHODS OF MANUFACTURE
A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one...
2018/0083008 MULTI-TIME PROGRAMMABLE (MTP) MEMORY CELLS, INTEGRATED CIRCUITS INCLUDING THE SAME, AND METHODS FOR FABRICATING...
Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an...
2018/0083007 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device...
2018/0083006 INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
An integrated circuit is provided, including: a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS...
2018/0083005 INTEGRATED CIRCUIT INCLUDING BALANCED CELLS LIMITING AN ACTIVE AREA
An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS...
2018/0083004 IMAGING DEVICE AND MANUFACTURING METHOD THEREOF
An imaging device includes: a semiconductor substrate; a first insulating layer covering a surface of the semiconductor substrate, the first insulating layer...
2018/0083003 Super-Self-Aligned Contacts and Method for Making the Same
A number of first hard mask portions are formed on a dielectric layer to vertically shadow a respective one of a number of underlying gate structures. A number...
2018/0083002 INTEGRATED CIRCUIT DEVICE WITH GATE LINE CROSSING FIN-TYPE ACTIVE REGION
An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active...
2018/0083001 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack...
2018/0083000 FIN EPITAXY WITH LATTICE STRAIN RELAXATION
A semiconductor having a first lattice constant is deposited on an exposed sidewall of a relatively small group IV semiconductor substrate fin having a second...
2018/0082999 INTEGRATED CIRCUITS WITH HIGH VOLTAGE DEVICES AND METHODS FOR PRODUCING THE SAME
Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes...
2018/0082998 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2018/0082997 VDMOS TRANSISTORS, BCD DEVICES INCLUDING VDMOS TRANSISTORS, AND METHODS FOR FABRICATING INTEGRATED CIRCUITS...
VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided....
2018/0082996 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD
It is aimed to realize both of reserving a channel formation region and suppressing a latch-up. A semiconductor device is provided, including: a semiconductor...
2018/0082995 INTEGRATED CIRCUITS HAVING TRANSISTORS WITH HIGH HOLDING VOLTAGE AND METHODS OF PRODUCING THE SAME
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a source in...
2018/0082994 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
An ESD protection device includes a semiconductor substrate of p-type conductivity, an epitaxial layer of p-type conductivity, a buried layer of n-type...
2018/0082993 OPTIMIZED CONFIGURATIONS TO INTEGRATE STEERING DIODES IN LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS)
A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated...
2018/0082992 INTEGRATED CIRCUIT WITH PROTECTION FROM TRANSIENT ELECTRICAL STRESS EVENTS AND METHOD THEREFOR
An integrated circuit with protection against transient electrical stress events includes a trigger circuit having a first detection circuit coupled to a first...
2018/0082991 SEMICONDUCTOR DEVICE
A semiconductor device includes a normally-on junction FET having a first gate electrode, a first source electrode and a first drain electrode, a normally-off...
2018/0082990 OPTICAL SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME
According to one embodiment, an optical semiconductor module is disclosed. The module includes an optical semiconductor. An electrode lead is arranged apart...
2018/0082989 THREE DIMENSIONAL INTEGRATED CIRCUIT
A stacked semiconductor device is formed by implanting ions through dielectric and conductive structures of a first substrate to define a cleave plane in the...
2018/0082988 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second...
2018/0082987 PACKAGE STRUCTURE WITH DUMMY DIE
A package structure and method for forming the same are provided. The package structure includes a substrate, and a device die formed over the substrate. The...
2018/0082986 LIGHT-EMITTING APPARATUS AND ILLUMINATION APPARATUS
A method of manufacturing a light-emitting apparatus includes mounting a first light-emitting element and a second light-emitting element on a substrate. A...
2018/0082985 LIGHT EMITTING DIODE PACKAGE AND LIGHT EMITTING DIODE MODULE
A light emitting diode package including a housing, a first light emitting diode chip and a second light emitting diode chip disposed in the housing, and a...
2018/0082984 DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE
The present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. The method of manufacturing a display substrate...
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