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Patent # Description
2018/0082983 SEMICONDUCTOR DEVICES WITH DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES AND METHODS OF MANUFACTURE
Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a...
2018/0082982 WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL...
A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two...
2018/0082981 INTEGRATED CIRCUIT DEVICES AND METHODS OF ASSEMBLING THE SAME
An integrated circuit (IC) device is described. The IC device includes a substrate. A connection component including a cavity therethrough is attached to the...
2018/0082980 PACKAGE MODULE, STACK STRUCTURE OF PACKAGE MODULE, AND FABRICATING METHODS THEREOF
A package module includes a power module, a first thermal dissipating component and a packaging plastic. The power module includes a substrate and at least one...
2018/0082979 Substrate and the Method to Fabricate Thereof
The present invention discloses a substrate where the lateral surface of the substrate is formed to expose at least one portion of a via(s) for circuit...
2018/0082978 Integrated Fan-Out Package Including Voltage Regulators and Methods Forming Same
A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and...
2018/0082977 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Reliability of a semiconductor device is improved. A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming...
2018/0082976 METHOD FOR WAFER-WAFER BONDING
A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor...
2018/0082975 METHOD OF JOINING A SURFACE-MOUNT COMPONENT TO A SUBSTRATE WITH SOLDER THAT HAS BEEN TEMPORARILY SECURED
A method of joining a surface-mount component to a substrate includes placing a piece of solder on top of the substrate and temporarily bonding the piece of...
2018/0082974 CIRCUIT PIN POSITIONING STRUCTURE, FABRICATION METHOD OF SOLDERED CIRCUIT ELEMENTS, AND METHOD OF FORMING...
The invention provides a circuit pin positioning structure, a fabrication method of soldered circuit elements and a method of forming circuit pins of a stacked...
2018/0082973 BONDING METHOD AND BONDED BODY
A bonding method of a first member and a second member includes: forming a first wire bonding bump (12) on a first electrode (14) arranged in the first member;...
2018/0082972 METHOD OF MANUFACTURING BONDED BODY
A method of manufacturing a bonded body in which a first body and a second body are bonded using a glass paste. The glass paste includes a crystallized glass...
2018/0082971 CONDUCTIVE ADHESIVE FILM STRUCTURES
Conductive adhesive films can include a binding material having a first set of conductive particles therewithin. The binding material can be electrically...
2018/0082970 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes...
2018/0082969 CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE
Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the...
2018/0082968 CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT
A method of fabricating a pillar-type connection includes forming a first conductive layer. A second conductive layer is formed on the first conductive layer...
2018/0082967 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface and a recess recessed from the first...
2018/0082966 Package with Passive Devices and Method of Forming the Same
An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device...
2018/0082965 MASKLESS SELECTIVE RETENTION OF A CAP UPON A CONDUCTOR FROM A NONCONDUCTIVE CAPPING LAYER
A semiconductor structure includes an electrically conductive structure formed upon an uppermost organic layer of a semiconductor substrate. A capping layer is...
2018/0082964 Semiconductor Package and Method of Forming the Same
An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer,...
2018/0082963 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad,...
2018/0082962 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2018/0082961 SEMICONDUCTOR DEVICE PACKAGE WITH WARPAGE CONTROL STRUCTURE
Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage...
2018/0082960 METALLIC, TUNABLE THIN FILM STRESS COMPENSATION FOR EPITAXIAL WAFERS
A metallic, stress-tunable thin film structure is applied to the backside of an epitaxial wafer to compensate for stress created by the frontside epitaxial...
2018/0082959 WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL...
A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at...
2018/0082958 THIN LOW DEFECT RELAXED SILICON GERMANIUM LAYERS ON BULK SILICON SUBSTRATES
A strain relaxed silicon germanium layer that has a low defect density is formed on a surface of a silicon substrate without causing wafer bowing. The strain...
2018/0082957 COBALT TOP LAYER ADVANCED METALLIZATION FOR INTERCONNECTS
An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern...
2018/0082956 COBALT TOP LAYER ADVANCED METALLIZATION FOR INTERCONNECTS
A method for constructing an advance conductor structure is described. A pattern is provided in a dielectric layer in which a set of features are patterned for...
2018/0082955 SELECTIVE SURFACE MODIFICATION OF INTERCONNECT STRUCTURES
Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a ...
2018/0082954 SEMICONDUCTOR PACKAGE
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an...
2018/0082953 TRENCH CONTACT RESISTANCE REDUCTION
A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer...
2018/0082952 FORMATION OF ADVANCED INTERCONNECTS
A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of...
2018/0082951 CONTACT HAVING SELF-ALIGNED AIR GAP SPACERS
A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed...
2018/0082950 TRENCH CONTACT RESISTANCE REDUCTION
A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer...
2018/0082949 FUSE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A fuse structure may include an anode pattern, a cathode pattern and a connection member. The anode pattern may be formed on a semiconductor substrate. The...
2018/0082948 NICKEL-SILICON FUSE FOR FINFET STRUCTURES
Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate....
2018/0082947 STRUCTURE OF INTEGRATED INDUCTOR
This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal...
2018/0082946 SURFACE NITRIDATION IN METAL INTERCONNECTS
Methods of forming vias include nitridizing exposed surfaces of a first layer and an exposed surface of a conductor underlying the first layer to form a layer...
2018/0082944 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
In a semiconductor device having a capacitive element, an increase in a leak current caused by the generation of a parasitic MOSFET is avoided by thinning the...
2018/0082943 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a...
2018/0082942 MICROELECTRONIC CONDUCTIVE ROUTES AND METHODS OF MAKING THE SAME
A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive...
2018/0082941 SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF
A substrate structure and its manufacturing method are provided. The substrate structure comprises a metal substrate, a first connection layer, a second...
2018/0082940 METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE INCLUDING A STAIR STEP STRUCTURE, AND RELATED SEMICONDUCTOR...
A method of forming a semiconductor device structure comprises forming a stack structure over a substrate, the stack structure comprising tiers each...
2018/0082939 PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING AN ELEMENT
The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one...
2018/0082938 RADIAL SOLDER BALL PATTERN FOR ATTACHING SEMICONDUCTOR AND MICROMECHANICAL CHIPS
A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example,...
2018/0082937 Microchip with Cap Layer for Redistribution Circuitry and Method of Manufacturing the Same
A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed...
2018/0082936 FAN-OUT PACKAGE STRUCTURE HAVING STACKED CARRIER SUBSTRATES AND METHOD FOR FORMING THE SAME
A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing...
2018/0082935 LOW CTE INTERPOSER
An interconnection component includes a first support portion, a second support portion, a redistribution layer and a passive device, wherein at least one of...
2018/0082934 SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first...
2018/0082933 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first...
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