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Patent # Description
2018/0082932 LAND STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD THEREFOR
A semiconductor package structure includes a substrate comprising a land structure. The land structure includes a first land section having a first height in a...
2018/0082931 LEAD FRAME AND ELECTRONIC COMPONENT DEVICE
A lead frame includes: a resin portion including an upper surface and a lower surface opposite to the upper surface; and a first terminal formed to penetrate...
2018/0082930 SYSTEM IN PACKAGE DEVICE INCLUDING INDUCTOR
Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first...
2018/0082929 DISPLAY PANEL AND DISPLAY DEVICE
A display panel and a display device are provided. The display panel comprises a first substrate having a step area; a second substrate disposed opposite to...
2018/0082928 MANUFACUTING METHOD OF SEMICONDUCTOR STRUCTURE
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in...
2018/0082927 SEMICONDUCTOR STRUCTURE AND MANUFACUTING METHOD OF THE SAME
The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in...
2018/0082926 COMPOSITE HEAT SINK STRUCTURES
Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a...
2018/0082925 Package cooled with cooling fluid and comprising shielding layer
A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer...
2018/0082924 HEAT DISSIPATION STRUCTURE, METHOD FOR MAKING THE SAME, AND ELECTRONIC DEVICE HAVING THE SAME
A heat dissipation structure comprises a flexible substrate, a graphite sheet, and a heat insulating material. The flexible substrate comprises a first surface...
2018/0082923 INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF
Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and...
2018/0082922 ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB
An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel...
2018/0082921 Package with roughened encapsulated surface for promoting adhesion
A package comprising at least one electronic chip, a first heat removal body thermally coupled to a first main surface of the at least one electronic chip and...
2018/0082920 POWER MODULE AND MANUFACTURING METHOD THEREOF
A power module includes: a substrate; a power conversion chip disposed on one surface of the substrate; and a radiation member bonded to another surface of the...
2018/0082919 ELECTRONIC PACKAGE COVER HAVING UNDERSIDE RIB
An electronic package lid which includes one or more underside ribs. The ribs have a major length and a minor width and are generally aligned to be parallel...
2018/0082918 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second...
2018/0082917 INFO STRUCTURE WITH COPPER PILLAR HAVING REVERSED PROFILE
A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first...
2018/0082916 FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTING
A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a...
2018/0082915 AIR CAVITY PACKAGES AND METHODS FOR THE PRODUCTION THEREOF
Air cavity packages and methods for producing air cavity packages containing sintered bonded components, multipart window frames, and/or other unique...
2018/0082914 GLASS SUBSTRATE AND LAMINATED SUBSTRATE
The present invention provides a glass substrate in which in a step of sticking a glass substrate and a silicon-containing substrate to each other, bubbles...
2018/0082913 HIGH RELIABILITY WAFER LEVEL SEMICONDUCTOR PACKAGING
Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an...
2018/0082912 FLAT LAMINATE, SYMMETRICAL TEST STRUCTURES AND METHOD OF USE TO GAUGE WHITE BUMP SENSITIVITY
A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is...
2018/0082911 SEMICONDUCTOR DEVICE AND METHOD OF UNIT SPECIFIC PROGRESSIVE ALIGNMENT
A semiconductor device and method can comprise measuring a true position of each of a plurality of semiconductor die within an embedded die panel and...
2018/0082910 LOW-COST SOI FINFET TECHNOLOGY
A method of forming an SOI fin using a porous semiconductor. The method may include forming a stack of semiconductor layers on a substrate, the stack includes...
2018/0082909 SACRIFICIAL CAP FOR FORMING SEMICONDUCTOR CONTACT
A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a...
2018/0082908 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first semiconductor channel, a second semiconductor channel, a first gate stack and a second gate stack. The first gate stack...
2018/0082907 Method for Manufacturing a Si-Based High-Mobility CMOS Device With Stacked Channel Layers, and Resulting Devices
A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate...
2018/0082906 NOVEL SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm
A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall...
2018/0082905 SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a...
2018/0082904 METHOD AND STRUCTURE FOR FORMING FINFET CMOS WITH DUAL DOPED STI REGIONS
A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the...
2018/0082903 METHOD OF PATTERNING INTERSECTING STRUCTURES
Provided is a method of patterning structures on a substrate using an integration scheme in a patterning system, the method comprising: disposing a substrate...
2018/0082902 FABRICATION OF NANO-SHEET TRANSISTORS WITH DIFFERENT THRESHOLD VOLTAGES
A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of...
2018/0082901 HIGH ASPECT RATIO CHANNEL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer....
2018/0082900 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY EPITAXIAL LIFT-OFF USING PLANE DEPENDENCY OF III-V COMPOUND
A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first...
2018/0082899 METHOD OF REMOVING A GROWTH SUBSTRATE FROM A LAYER SEQUENCE
A method of detaching a growth substrate from a layer sequence includes introducing at least one wafer composite into an etching bath containing an etching...
2018/0082898 Methods for Splitting Semiconductor Devices and Semiconductor Device
A method for splitting a semiconductor wafer includes incorporating hydrogen atoms into at least a splitting region of a semiconductor wafer. The splitting...
2018/0082897 PROCESSING METHOD FOR WAFER
A wafer has a front face that is partitioned by a plurality of streets crossing with each other into a plurality of regions in each of which a device is...
2018/0082896 Encapsulated Semiconductor Package and Method of Manufacturing Thereof
Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a...
2018/0082895 SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME
According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate;...
2018/0082894 INTERCONNECT STRUCTURE
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
2018/0082893 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes...
2018/0082892 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided herein is a method of manufacturing a semiconductor device. The method may include forming an amorphous channel layer. The method may include forming...
2018/0082891 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process....
2018/0082890 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device and a fabricating method thereof are provided. The method includes sequentially forming an interlayer insulating layer and a hard mask...
2018/0082889 FDSOI CHANNEL CONTROL BY IMPLANTED HIGH-K BURIED OXIDE
Methods of locally changing the BOX layer of a MOSFET device to a high-k layer to provide different Vts with one backside voltage and the resulting device are...
2018/0082888 WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT, AND THERMAL...
A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two...
2018/0082887 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A photoresist pattern is not formed in an outer circumferential region from an outer circumferential end of a semiconductor substrate up to 0.5 mm to 3.0 mm,...
2018/0082886 TEMPORALLY PULSED AND KINETICALLY MODULATED CVD DIELECTRICS FOR GAPFILL APPLICATIONS
A method for performing temporally pulsed chemical vapor deposition (CVD) is provided, including: providing a first reactant configured to adsorb on exposed...
2018/0082885 SELF-ALIGNED AIRGAPS WITH CONDUCTIVE LINES AND VIAS
A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric...
2018/0082884 PROCESS FOR MAKING A SEMICONDUCTOR SYSTEM
This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two...
2018/0082883 FETS and Methods of Forming FETS
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation...
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