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Patent # Description
2018/0082882 Wafer Chuck, Use of the Wafer Chuck and Method for Testing a Semiconductor Wafer
A wafer chuck configured to support a wafer during a wafer test procedure comprises a contact portion for supporting the wafer while being in contact with the...
2018/0082881 SUBSTRATE PROCESSING APPARATUS AND METHOD OF TRANSFERRING SUBSTRATE
There is provided a substrate processing apparatus having a transfer arm configured to transfer two substrates between a transfer chamber and a processing...
2018/0082880 SUBSTRATE HOLDING APPARATUS
A substrate holding apparatus includes a placing portion, a first depressurization unit, a second depressurization unit, a storage unit and a control unit. The...
2018/0082879 Substrate transfer apparatus and control method thereof
Provided are a substrate transfer apparatus and a control method thereof. The substrate transfer apparatus includes a body having a gate through which a...
2018/0082878 CLUSTER TOOL APPARATUS AND A METHOD OF CONTROLLING A CLUSTER TOOL APPARATUS
A system and method for a cluster tool apparatus for processing a semiconductor product including processing modules located adjacent each other and configured...
2018/0082877 Wafer Transport System
A transport system includes, in a first environment, a driving screw having threads with a thread pitch. In a second environment, a driven member has a...
2018/0082876 METHOD FOR CHARGING GAS INTO CASSETTE POD
A method for transporting a cassette pod for containing semiconductor waters is provided. The method includes transporting a cassette pod configured to receive...
2018/0082875 SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE TRANSFER METHOD
A substrate processing apparatus includes: a substrate conveyance area; a substrate storage conveyance area; a substrate storage storing shelf; a first purge...
2018/0082874 METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL
Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a...
2018/0082873 SEARCH APPARATUS AND SEARCH METHOD
A search apparatus receives an input target value, which indicates a condition to be set in a semiconductor processing apparatus or a result obtained by...
2018/0082872 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
The present invention provides a semiconductor device manufacturing method that can sense the atmospheric air leakage more precisely and that can prevent too...
2018/0082871 GAS FLOW PROCESS CONTROL SYSTEM AND METHOD USING CRYSTAL MICROBALANCE(S)
Disclosed are process control systems and methods incorporating a crystal microbalance (CM) (e.g., a quartz crystal microbalance (QCM)) into gas flow line(s)...
2018/0082870 ASSEMBLIES AND METHODS OF PROCESS GAS FLOW CONTROL
Gas flow control assemblies configured to deliver a gas to a process chamber. The gas flow control assemblies include a single-piece manifold including a...
2018/0082869 SUBSTRATE PROCESSING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device...
2018/0082868 GRAVITY FORCE COMPENSATION PLATE FOR UPSIDE DOWN BALL GRID ARRAY
An apparatus configured to temporarily support a Ball Grid Array (BGA) component against a printed circuit board (PCB) during a manufacturing reflow operation,...
2018/0082867 UNIVERSAL LOAD PORT FOR ULTRAVIOLET RADIATION SEMICONDUCTOR WAFER PROCESSING MACHINE
A semiconductor cassette universal load port. The universal load port comprises a frame, three pins coupled to the frame forming a first portion of a kinematic...
2018/0082866 HEATER PEDESTAL ASSEMBLY FOR WIDE RANGE TEMPERATURE CONTROL
Implementations of the disclosure generally relate to a semiconductor processing chamber and, more specifically, a heated support pedestal for a semiconductor...
2018/0082865 HEATING APPARATUS, SUBSTRATE HEATING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A heating apparatus includes a heater, an electron reflection plate, a filament arranged between the heater and the electron reflection plate, a heating power...
2018/0082864 GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING
A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding...
2018/0082863 GAS-CONTROLLED BONDING PLATFORM FOR EDGE DEFECT REDUCTION DURING WAFER BONDING
A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding...
2018/0082862 SUBSTRATE PROCESSING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A substrate processing device includes a bath configured to accommodate a plurality of substrates and configured to store a liquid for etching the plurality of...
2018/0082861 SELECTIVE ETCH USING MATERIAL MODIFICATION AND RF PULSING
Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The...
2018/0082860 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus has a cup part for receiving processing liquid such as pure water which is splashed from a substrate. The cup part is formed...
2018/0082859 SUBSTRATE PROCESSING METHOD
A substrate processing method in a substrate processing apparatus that has a cup part for receiving processing liquid such as pure water which is splashed from...
2018/0082858 CARRIER ULTRA THIN SUBSTRATE
Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface...
2018/0082857 ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED ELECTRONICS PACKAGE
An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled...
2018/0082855 PLASMA PROCESSING METHOD
The present invention provides a plasma processing method for subjecting a sample on which a metal element-containing film is disposed to plasma etching in a...
2018/0082854 METAL FILL OPTIMIZATION FOR SELF-ALIGNED DOUBLE PATTERNING
A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal...
2018/0082853 Method of Planarising a Surface
In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region including at least one compound...
2018/0082852 FIN PATTERNING FOR A FIN-TYPE FIELD-EFFECT TRANSISTOR
Methods for fabricating fins for a fin-type field-effect transistor (FinFET) and fin structures for a FinFET. A conformal layer is formed that includes...
2018/0082851 SPACER FORMATION FOR SELF-ALIGNED MULTI-PATTERNING TECHNIQUE
Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a...
2018/0082850 SELF-ALIGNED SINGLE DUMMY FIN CUT WITH TIGHT PITCH
A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor...
2018/0082849 METHODS FOR SELECTIVE ETCHING OF A SILICON MATERIAL USING HF GAS WITHOUT NITROGEN ETCHANTS
The present disclosure provides methods for etching a silicon material in a device structure in semiconductor applications. In one example, a method for...
2018/0082848 ELECTRONIC DEVICE, ELECTRONIC MODULE AND METHODS FOR FABRICATING THE SAME
An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic...
2018/0082847 PLASMA TREATING A PROCESS CHAMBER
Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon...
2018/0082846 LAYOUT EFFECT MITIGATION IN FINFET
Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor...
2018/0082845 METAL CAP INTEGRATION BY LOCAL ALLOYING
A middle-of-line interconnect structure including copper interconnects and integral copper alloy caps provides effective electromigration resistance. A metal...
2018/0082844 TECHNIQUES FOR FORMING PATTERNED FEATURES USING DIRECTIONAL IONS
A method of patterning a substrate. The method may include: providing a first surface feature and a second surface feature in a staggered configuration within...
2018/0082843 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat...
2018/0082842 METHOD OF IN SITU HARD MASK REMOVAL
Systems and methods for in situ hard mask removal are described. In an embodiment, a method includes receiving a semiconductor workpiece comprising a...
2018/0082841 SILICON CARBIDE SEMICONDUCTOR SUBSTRATE, METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR SUBSTRATE,...
A silicon carbide semiconductor substrate includes a silicon carbide substrate of a first conductivity type, an epitaxial layer of the first conductivity type...
2018/0082840 Metal oxide-resistive memory using two-dimensional edge electrodes
Improved resistive random access memory (RRAM) devices are provided that use a 2-D electrode as the SET electrode to take up a variable amount of oxygen from...
2018/0082839 METHOD FOR MANUFACTURING FERROELECTRIC THIN FILM DEVICE
This method for manufacturing a ferroelectric thin film device includes: a lower electrode film formation step of forming a lower electrode film on a...
2018/0082838 ATOMIC LAYER DEPOSITION OF SILICON CARBON NITRIDE BASED MATERIALS
A process for depositing a silicon carbon nitride film on a substrate can include a plurality of complete deposition cycles, each complete deposition cycle...
2018/0082837 METHOD TO INCREASE STRAIN IN A SEMICONDUCTOR REGION FOR FORMING A CHANNEL OF THE TRANSISTOR
Realisation of a device comprising a transistor channel strained semiconductor structure, comprising: a) the formation, on a strained semiconductor layer, of a...
2018/0082836 INTEGRATED SYSTEM AND METHOD FOR SOURCE/DRAIN ENGINEERING
Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching...
2018/0082835 UV RADIATION SYSTEM AND METHOD FOR ARSENIC OUTGASSING CONTROL IN SUB 7NM CMOS FABRICATION
Implementations disclosed herein relate to methods for controlling substrate outgassing of hazardous gasses after an epitaxial process. In one implementation,...
2018/0082834 METHOD AND SYSTEM FOR WET CHEMICAL BATH PROCESS
A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical...
2018/0082833 BACK-SIDE FRICTION REDUCTION OF A SUBSTRATE
A processing chamber system includes a substrate mounting module configured to secure a substrate within a first processing chamber. The system also includes a...
2018/0082832 APPARATUS AND METHOD OF TREATING SURFACE OF SEMICONDUCTOR SUBSTRATE
In one embodiment, an apparatus of treating a surface of a semiconductor substrate comprises a substrate holding and rotating unit, first to fourth supplying...
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