Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0090610 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode...
2018/0090609 ACTIVE DEVICE AND METHOD FOR MANUFACTURING ACTIVE DEVICE
[Object] The present invention provides an active device in which the misalignment of a partition relative to electrodes is reduced and a method for ...
2018/0090608 FinFET with Rounded Source/Drain Profile
A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a...
2018/0090607 FinFET Device
A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric...
2018/0090606 FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed...
2018/0090605 IFINFET
A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and ...
2018/0090604 FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed...
2018/0090603 COMPOUND SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREFOR, COMPOUND SEMICONDUCTOR DEVICE AND FABRICATION...
A compound semiconductor substrate includes a substrate, a channel layer provided over the substrate, a nitride semiconductor layer provided over the channel...
2018/0090602 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE
The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source...
2018/0090601 THIN-FILM TRANSISTOR (TFT) AND MANUFACTURING METHOD THEREOF
A thin-film transistor (TFT) and a manufacturing method thereof. The manufacturing method for the TFT includes: depositing metal film layers on a substrate by...
2018/0090600 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
A semiconductor device may include a nitride semiconductor layer, an insulation gate section, and a heterojunction region, wherein the nitride semiconductor...
2018/0090599 FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the...
2018/0090598 CONTROLLING SELF-ALIGNED GATE LENGTH IN VERTICAL TRANSISTOR REPLACEMENT GATE FLOW
A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a...
2018/0090597 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
The reliability of a semiconductor device is improved. A first gate electrode of a dummy gate electrode including silicon is formed over a semiconductor...
2018/0090596 SEMICONDUCTOR DEVICE INCLUDING OPTIMIZED GATE STACK PROFILE
A semiconductor device is provided with an electrically conductive gate having an enhanced gate profile. The semiconductor device includes a semiconductor...
2018/0090595 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, POWER UNIT, AND AMPLIFIER
A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed...
2018/0090594 Method of Manufacturing a Semiconductor Device Having Electrode Trenches, Isolated Source Zones and Separation...
A semiconductor device includes a semiconductor mesa having source zones and at least one body zone forming first pn junctions with the source zones and a...
2018/0090593 TRANSISTOR WITH AIR SPACER AND SELF-ALIGNED CONTACT
A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method...
2018/0090591 FERROELECTRIC GATE DIELECTRIC WITH SCALED INTERFACIAL LAYER FOR STEEP SUB-THRESHOLD SLOPE FIELD-EFFECT TRANSISTOR
A method is presented for forming a semiconductor device. The method includes forming an oxygen containing interfacial layer on a semiconductor substrate,...
2018/0090590 Metal Gate Process for FinFET Device Improvement
In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to...
2018/0090589 SEMICONDUCTOR DEVICE BLOCKING LEAKAGE CURRENT AND METHOD OF FORMING THE SAME
A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact...
2018/0090588 AIR GAP AND AIR SPACER PINCH OFF
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a...
2018/0090587 AIR GAP AND AIR SPACER PINCH OFF
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a...
2018/0090586 TRANSISTOR WITH AIR SPACER AND SELF-ALIGNED CONTACT
A method of fabricating a semiconductor transistor and the semiconductor transistor include a source region and a drain region within a substrate. The method...
2018/0090585 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal...
2018/0090584 SEMICONDUCTOR DEVICE
A nitride semiconductor device is disclosed, where the nitride semiconductor device type of a field effect transistor having a gate electrode and an insulating...
2018/0090583 Semiconductor Devices Having Reduced Contact Resistance
A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an...
2018/0090582 LOW RESISTIVITY WRAP-AROUND CONTACTS
Low resistivity, wrap-around contact structures are provided in nanosheet devices, vertical FETs, and FinFETs. Such contact structures are obtained by...
2018/0090581 VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES
Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold...
2018/0090580 FIELD EFFECT TRANSISTOR HAVING ELECTRODE COATED SEQUENTIALLY BY OXIDE LAYER AND NITRIDE LAYER AND METHOD FOR...
A field effect transistor includes a substrate, an epitaxial layer, a remnant-oxide layer, an electrode, a surrounding-oxide layer, a surrounding-nitride...
2018/0090579 UNIFORM VERTICAL FIELD EFFECT TRANSISTOR SPACERS
Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls,...
2018/0090578 Controlling Method of a Transistor of Type IGBT and Associated Controlling Device
This method for controlling an IGBT-type transistor includes a phase for switching the transistor between an on state and an off state. Said phase comprises...
2018/0090577 COMPOUND SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE, POWER SUPPLY UNIT, AND...
A compound semiconductor device disclosed herein includes a substrate, an electron transit layer formed on the substrate, a compound semiconductor layer...
2018/0090576 LASER DEVICE INTEGRATED WITH SEMICONDUCTOR OPTICAL AMPLIFIER ON SILICON SUBSTRATE
A laser device includes a silicon substrate, a buffer layer on the silicon substrate, a laser cavity on the buffer layer including a first active region based...
2018/0090575 COMPOUND SEMICONDUCTOR DEVICE, POWER SUPPLY UNIT, AND AMPLIFIER
A compound semiconductor device disclosed herein includes: a substrate; an electron transit layer formed on the substrate and made of nitride semiconductor...
2018/0090574 SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE
To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to...
2018/0090573 TENSILE STRAINED NFET AND COMPRESSIVELY STRAINED PFET FORMED ON STRAIN RELAXED BUFFER
A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate....
2018/0090572 THYRISTOR WITH IMPROVED PLASMA SPREADING
There is provided a thyristor having emitter shorts, wherein in an orthogonal projection onto a plane parallel to a first main side, a contact area covered by...
2018/0090571 SEMICONDUCTOR DEVICE
A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the...
2018/0090570 Strained Nanowire CMOS Device and Method of Forming
Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial...
2018/0090569 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first...
2018/0090568 PROCESS FOR FABRICATING SILICON NANOSTRUCTURES
A process for etching a substrate comprising polycrystalline silicon to form silicon nanostructures includes depositing metal on top of the substrate and...
2018/0090567 FINFET DEVICES
FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of...
2018/0090566 NANOSHEET ISOLATION FOR BULK CMOS NON-PLANAR DEVICES
A semiconductor structure is provided that includes a semiconductor substrate including a first device region and a second device region. First trench...
2018/0090565 Semiconductor Device and Method for Forming a Semiconductor Device
A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes...
2018/0090564 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND POWER CONVERSION SYSTEM
An anode electrode and a cathode electrode formed on a silicon semiconductor substrate, p-type layer formed next to the anode electrode, an n-type layer formed...
2018/0090563 SEMICONDUCTOR DEVICE
In an ESD protection element configured to protect a semiconductor device, a first N-type low concentration diffusion layer is formed, as an offset layer for...
2018/0090562 SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME
A Schottky barrier diode includes an epitaxial layer of a first conductivity type and located on a substrate, a first well of a second conductivity type and...
2018/0090561 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACK
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2018/0090560 ON-CHIP MIM CAPACITOR
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.