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Patent # Description
2018/0090508 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1...
2018/0090507 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device includes a stacked body and an insulating portion. The stacked body includes first to fourth electrode layers. The first electrode layer...
2018/0090506 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An...
2018/0090505 Method for producing integrated circuit memory cells with less dedicated lithographic steps
Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of...
2018/0090504 MASK-PROGRAMMABLE ROM USING A VERTICAL FET INTEGRATION PROCESS
A mask programmable read-only memory (PROM) cell is provided utilizing a vertical transistor processing flow. PROM programming is performed during the...
2018/0090503 EMBEDDED MEMORY WITH ENHANCED CHANNEL STOP IMPLANTS
An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer....
2018/0090502 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Described herein is a technique capable of suppressing the deviation in the characteristic of the semiconductor device. A method of manufacturing a...
2018/0090501 SEMICONDUCTOR DEVICE
A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM...
2018/0090500 SEMICONDUCTOR ARRANGEMENT WITH CAPACITOR AND METHOD OF FABRICATING THE SAME
A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor...
2018/0090499 SEMICONDUCTOR DEVICE
An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on...
2018/0090498 SEMICONDUCTOR DEVICE
To provide a semiconductor device in which the on-state current is high and the operation speed is high. The semiconductor device includes a transistor, a...
2018/0090497 MULTI-THRESHOLD VOLTAGE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
The present disclosure provides an FET structure including a transistor of a first conductive type. The transistor includes a substrate having a region of a...
2018/0090496 MULTIPLE FINFET FORMATION WITH EPITAXY SEPARATION
A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate...
2018/0090495 Semiconductor Devices Including Active Areas with Increased Contact Area
Semiconductor devices may have a first semiconductor element including first active regions that are doped with a first conductivity-type impurity and that are...
2018/0090494 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
A method of forming a semiconductor device, includes forming first and second SiGe fins on a substrate, forming a protective layer on the first SiGe fin,...
2018/0090493 SEMICONDUCTOR DEVICES INCLUDING A DEVICE ISOLATION REGION IN A SUBSTRATE AND/OR FIN
Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate. The semiconductor device includes first and second source/drain...
2018/0090492 INTEGRATED CIRCUIT (IC) DEVICES INCLUDING CROSS GATE CONTACTS
Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending...
2018/0090491 FinFET Cut-Last Process Using Oxide Trench Fill
A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is...
2018/0090490 Switching Field Plate Power MOSFET
A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a...
2018/0090489 ASYMMETRICAL VERTICAL TRANSISTOR
A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor...
2018/0090488 INTEGRATED LDMOS AND VFET TRANSISTORS
Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect...
2018/0090487 SEMICONDUCTOR DEVICE
A semiconductor device includes a multilayer structure including an n- i layer, a p anode layer formed on the front surface of the n- i layer, an n- buffer...
2018/0090486 ON-CHIP MIM CAPACITOR
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate...
2018/0090485 BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION
Integrated chips includes a first transistor and a second transistor. The first transistor includes a first semiconductor fin having a channel region and a...
2018/0090484 ELECTROSTATIC DISCHARGE DEVICES AND METHODS OF MANUFACTURE
Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure...
2018/0090483 Microelectronic device with protective circuit
Microelectronic devices are formed on a substrate of an integrated circuit. An electrically conductive ground or power plane, and an Electro Static Discharge...
2018/0090482 Electrostatic Discharge Protection Circuit Applied in Integrated Circuit
The present application provides an electrostatic discharge protection circuit including a first N-type transistor, a second N-type transistor and a...
2018/0090481 ELECTROSTATIC DISCHARGE CIRCUIT AND MANUFACTURING METHODS THEREOF
An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the...
2018/0090480 SEMICONDUCTOR DEVICE
An electrostatic protection element whose electrostatic breakdown resistance can be adjusted with a required minimum design change is provided. A...
2018/0090479 Semiconductor Devices and Methods for Forming a Semiconductor Device
A semiconductor device includes a transistor arrangement and a diode structure. The diode structure is coupled between a gate electrode structure of the...
2018/0090478 LED MODULE AND METHOD OF MANUFACTURING THE SAME
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead,...
2018/0090477 TRANSIENT VOLTAGE SUPPRESSOR AND METHOD FOR MANUFACTURING THE SAME
Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer...
2018/0090476 COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A compound semiconductor device includes transistors each including a gate electrode, a source electrode, and a drain electrode, wherein out of the...
2018/0090475 BACKSIDE GROUND PLANE FOR INTEGRATED CIRCUIT
An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate...
2018/0090474 INTERCONNECTION OF AN EMBEDDED DIE
Devices and methods related to an integrated circuit device are provided. The integrated circuit device includes a mother die and a daughter die, in which the...
2018/0090473 SEMICONDUCTOR MODULE
It is an object of the present invention to provide a semiconductor module in which a bonded portion has high reliability, and that has a small area. A...
2018/0090472 INTEGRATED III-V DEVICE AND DRIVER DEVICE UNITS AND METHODS FOR FABRICATING THE SAME
Integrated circuits, wafer level integrated III-V device and CMOS driver device packages, and methods for fabricating products with integrated III-V devices...
2018/0090471 Package on Package Structure Having Package To Package Interconnect Composed of Packed Wires Having A Polygon...
An apparatus is described that includes a package on package structure. The package on package structure includes an interposer to implement electrical...
2018/0090470 LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME
A light emitting device includes a substrate, a plurality of light emitting elements disposed on the substrate, a transparent resin embedded in a space between...
2018/0090469 SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR PRODUCING THE SAME
A light-emitting device having a plurality of light-emitting elements closely adjacently disposed in spite of using only one substrate is provided. One or...
2018/0090468 INTEGRATED CIRCUIT PACKAGE ASSEMBLY WITH WIRE END ABOVE A TOPMOST COMPONENT
Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in...
2018/0090467 PACKAGE WITH THERMAL COUPLING
Embodiments herein relate to thermal coupling using through mold vias (TMV). Embodiments may include a substrate having a first side and a second side opposite...
2018/0090466 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes a substrate, electronic components disposed over a surface of the substrate, an encapsulant encapsulating the...
2018/0090465 Discrete Polymer in Fan-Out Packages
A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the...
2018/0090464 WIRE BONDING APPARATUS AND WIRE BONDING METHOD
In order to easily and accurately measure an offset for wire bonding and improve precision of wire bonding, a wiring bonding apparatus includes a first imaging...
2018/0090463 SEMICONDUCTOR DEVICE HAVING LOW ON RESISTANCE
A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers...
2018/0090462 INTEGRATED CIRCUIT PACKAGE HAVING RECTANGULAR ASPECT RATIO
An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body...
2018/0090461 SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal...
2018/0090460 WAFER LEVEL PACKAGE AND METHOD
A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the...
2018/0090459 FILM-TYPE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A film-type semiconductor package includes a metal lead portion arranged on a film substrate, a semiconductor chip including a pad, and a bump connecting the...
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