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Patent # Description
2018/0090407 FLIP CHIP BALL GRID ARRAY WITH LOW IMPEDNCE AND GROUNDED LID
A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device...
2018/0090406 FLIP CHIP BALL GRID ARRAY WITH LOW IMPEDNCE AND GROUNDED LID
A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device...
2018/0090405 ELECTRONIC COMPONENT STORAGE SUBSTRATE AND HOUSING PACKAGE
The present invention includes: a substrate 3, a rectangular frame-shaped substrate bank section 5 provided on the substrate 3 and including four corner...
2018/0090404 ELECTROLYTIC SEAL
A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first...
2018/0090403 ELECTROLYTIC SEAL
A semiconductor device includes a first bonding surface disposed on a first component of the semiconductor device. A bond material is disposed on the first...
2018/0090402 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an...
2018/0090401 SEMICONDUCTOR DEVICE
A semiconductor device comprises two electrodes with opposite faces; a semiconductor wafer sandwiched between the two electrodes; an outer insulating ring...
2018/0090400 METHOD OF FORMING A TEMPORARY TEST STRUCTURE FOR DEVICE FABRICATION
A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during...
2018/0090399 METHOD OF FORMING A TEMPORARY TEST STRUCTURE FOR DEVICE FABRICATION
A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during...
2018/0090398 DISPLAY DEVICE INCLUDING AN ADHESIVE LAYER
A display device includes a display panel having a display area and a non-display area. A window is disposed on the display panel. A bezel portion is disposed...
2018/0090397 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes: processing a substrate by operating a processing apparatus included in a substrate processing...
2018/0090396 SYSTEM AND METHOD FOR DETECTING SUBSTRATE AND MANUFACTURING DEVICE
A system and a method for detecting a substrate and a manufacturing device are disclosed. The detection system includes: an emitting unit and a control unit;...
2018/0090395 SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
A bonding machine for bonding semiconductor elements, the bonding machine including: a support structure for supporting a substrate; a bond head assembly, the...
2018/0090394 PRESSURE-ACTIVATED ELECTRICAL INTERCONNECTION BY MICRO-TRANSFER PRINTING
A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one...
2018/0090393 METHOD AND ARRANGEMENT FOR ANALYZING A SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT
According to the improved concept, a method for analyzing a semiconductor element comprising polymer residues located on a surface of the semiconductor element...
2018/0090392 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING DEEP WELLS
A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation...
2018/0090391 METHODS, APPARATUS AND SYSTEM FOR SELF-ALIGNED RETROGRADE WELL DOPING FOR FINFET DEVICES
At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal...
2018/0090390 SEMICONDUCTOR DEVICES WITH SIDEWALL SPACERS OF EQUAL THICKNESS
Semiconductor structures with different devices each having spacers of equal thickness and methods of manufacture are disclosed. The method includes forming a...
2018/0090389 INTEGRATED CIRCUIT COMPRISING MOS TRANSISTORS AND METHOD OF MANUFACTURING THE SAME
An integrated circuit includes FDSOI-type MOS transistors formed inside and on top of a semiconductor layer resting on an insulating layer. The transistors...
2018/0090388 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and...
2018/0090387 METHOD FOR FORMING NANOWIRES INCLUDING MULTIPLE INTEGRATED DEVICES WITH ALTERNATE CHANNEL MATERIALS
Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first...
2018/0090386 PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES
In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance,...
2018/0090385 HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES
A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer...
2018/0090384 HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES
A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer...
2018/0090383 STACK TYPE SEMICONDUCTOR MEMORY DEVICE
A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of...
2018/0090382 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device comprises a step of ion-implanting a P-type impurity at a first dose amount to form semiconductor regions that...
2018/0090381 INTEGRATED METAL GATE CMOS DEVICES
A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second...
2018/0090380 BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION
Methods of forming integrated chips include forming a gate stack around a first semiconductor fin and a second semiconductor fin. The gate stack around the...
2018/0090379 WAFER DICING METHOD
A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a...
2018/0090378 ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE
An array substrate and a method for manufacturing the same, and a display device are provided. The method includes: forming a thin film transistor (TFT)...
2018/0090377 ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, a signal line disposed...
2018/0090376 ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY PANEL AND DISPLAY DEVICE
The present disclosure provides an array substrate and a method of manufacturing the same, a display panel and a display device. The array substrate is...
2018/0090375 SELF-ALIGNED LOW DIELECTRIC CONSTANT GATE CAP AND A METHOD OF FORMING THE SAME
According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate;...
2018/0090374 TWO-DIMENSIONAL SELF-ALIGNED SUPER VIA INTEGRATION ON SELF-ALIGNED GATE CONTACT
Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal...
2018/0090373 THREE-DIMENSIONAL MEMORY DEVICE CONTAINING WORD LINES FORMED BY SELECTIVE TUNGSTEN GROWTH ON NUCLEATION...
A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory...
2018/0090372 HETEROGENEOUS METALLIZATION USING SOLID DIFFUSION REMOVAL OF METAL INTERCONNECTS
A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width....
2018/0090371 INTERCONNECT STRUCTURE
Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect...
2018/0090370 Directional Patterning Methods
Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a...
2018/0090369 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A...
2018/0090368 ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches...
2018/0090367 HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES
A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense...
2018/0090366 INTEGRATED CIRCUIT HAVING A PLURALITY OF ACTIVE LAYERS AND METHOD OF FABRICATING THE SAME
A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of...
2018/0090365 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
When a void is caused in an interlayer insulating film on a semiconductor substrate, the invention prevents short circuit between two or more contact plugs...
2018/0090364 SUBSTRATE PROCESSING APPARATUS, TRANSFER METHOD, AND SUSCEPTOR
An apparatus of an embodiment includes: a processing-chamber; a susceptor capable of supporting a substrate, the susceptor including a first member having an...
2018/0090363 LIFT PIN HOLDER WITH SPRING RETENTION FOR SUBSTRATE PROCESSING SYSTEMS
A lift pin holder assembly includes a lift pin holder including a central bore defining a first groove arranged on a radially inner surface of the central...
2018/0090362 FLUORO-SILICONE COMPOSITIONS AS TEMPORARY BONDING ADHESIVES
Fluoro-containing silicone-based storage stable temporary bonding adhesive compositions are disclosed. The adhesive compositions can be used in varied...
2018/0090361 MOUNTING TABLE AND PLASMA PROCESSING APPARATUS
A mounting table, to which a voltage is applied, includes an electrostatic chuck having a mounting surface for mounting a target object and a rear surface...
2018/0090360 SUBSTRATE ALIGNMENT APPARATUS, SUBSTRATE PROCESSING APPARATUS, SUBSTRATE ARRANGEMENT APPARATUS, SUBSTRATE...
In a substrate alignment apparatus, a motor sequentially rotates a plurality of substrates in a circumferential direction, the substrates being to be held in a...
2018/0090359 SUBSTRATE ARRANGEMENT APPARATUS AND SUBSTRATE ARRANGEMENT METHOD
In a substrate arrangement apparatus, a holder elevating mechanism disposes each first substrate between each pair of second substrates, with the first and...
2018/0090358 POSTURE CHANGING DEVICE
A posture changing device changes the posture of a substrate from one of horizontal and vertical postures to the other posture. In the posture changing device,...
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