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Patent # Description
2018/0089141 DATA PROCESSING DEVICE
A data processing device includes a two-dimensional structure including a plurality of stages in a vertical direction, the stages each including basic units in...
2018/0089140 Pipelined Configurable Processor
A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable...
2018/0089139 HYBRID PROGRAMMABLE MANY-CORE DEVICE WITH ON-CHIP INTERCONNECT
The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core...
2018/0089138 APPLICATION ARCHITECTURE SUPPORTING MULTIPLE SERVICES AND CACHING
A service agent provides an interface for the actions that a client application needs to perform against a server. The service agent selects an appropriate...
2018/0089137 LOW OVERHEARD HIGH THROUGHPUT SOLUTION FOR POINT-TO-POINT LINK
An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support...
2018/0089136 SIMULTANEOUS INBOUND MULTI-PACKET PROCESSING
A system includes an input/output adapter operable to receive packets in a single clock cycle. The system includes a controller operatively connected to the...
2018/0089135 Library for Seamless Management of Storage Devices
An approach for using a storage library to translate commands from one command language into a different command language. The approach includes receiving a...
2018/0089134 OPERATING SYSTEM CARD FOR MULTIPLE DEVICES
In one general aspect, a main printed circuit board (PCB) card can include a System on a Chip (SoC) configured to run an operating system stored on the main...
2018/0089133 FAIL FUNCTIONAL AUTOMATED DRIVING
A vehicle system includes a first communication path and a second communication path. The vehicle system further includes a processor programmed to determine a...
2018/0089132 CONFIGURABLE LOGIC PLATFORM
The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable...
2018/0089131 PHYSICAL CONFIGURATION OF A DEVICE FOR INTERACTION MODE SELECTION
In various embodiments, methods and systems are provide for detecting a physical configuration of a device based on sensor data from one or more configuration...
2018/0089130 SELECTIVELY UPGRADEABLE DISAGGREGATED SERVER
A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor...
2018/0089129 COMPUTER SYSTEM AND A COMPUTER DEVICE
A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller...
2018/0089128 RECONFIGURABLE FABRIC DIRECT MEMORY ACCESS WITH MULTIPLE READ OR WRITE ELEMENTS
Techniques are disclosed for data manipulation. Data is obtained from a first switching element where the first switching element is controlled by a first...
2018/0089127 TECHNOLOGIES FOR SCALABLE HIERARCHICAL INTERCONNECT TOPOLOGIES
Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each...
2018/0089126 MITIGATION OF SIDE EFFECTS OF SIMULTANEOUS SWITCHING OF INPUT/OUTPUT (I/O DATA SIGNALS
An apparatus and method may detect and reduce noise on data busses by adjusting the phase of the input/output (I/O) signals in a controlled, predictable...
2018/0089125 System Level Crosstalk Mitigation
An information handling system includes a receiver and a transmitter. A margin detector of the receiver derives an eye plot for signals received via a...
2018/0089124 MULTI-PACKET PROCESSING WITH ORDERING RULE ENFORCEMENT
A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively...
2018/0089123 SB TYPE C DUAL-ROLE-PORT UNATTACHED DUTY CYCLE RANDOMIZATION
Disclosed is a universal serial bus (USB) circuit, comprising including a USB interface configured to transmit and receive power and data, a random number...
2018/0089122 SYSTEM, APPARATUS AND METHOD FOR PERFORMING DISTRIBUTED ARBITRATION
In one embodiment, a distributed arbitration system for an interconnect includes: a first transmitter to output first data and a transmit identifier associated...
2018/0089121 DATA TRANSFER DEVICE AND WIRELESS COMMUNICATION CIRCUIT
Provided is a data transfer device that reduces generation of noise caused by an unnecessary transfer of a serial clock signal. The data transfer device...
2018/0089120 SYSTEMS AND METHODS FOR DEVICE COMMUNICATIONS
Systems and methods for improvement in bus communications with daisy-chained connected devices are described herein. In some embodiments, a bus communication...
2018/0089119 CONFIGURABLE LOGIC PLATFORM WITH MULTIPLE RECONFIGURABLE REGIONS
The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of...
2018/0089118 METHODS AND APPARATUS FOR AGGREGATING PACKET TRANSFER OVER A VIRTUAL BUS INTERFACE
Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments...
2018/0089117 RECONFIGURABLE FABRIC ACCESSING EXTERNAL MEMORY
Techniques are disclosed for data manipulation. A memory request is initiated from a first cluster within a reconfigurable fabric. The memory request is queued...
2018/0089116 ELECTRONIC DEVICE PROVIDING BYPASS PATH TO INDIRECTLY CONNECTED STORAGE DEVICE AMONG SERIALLY CONNECTED STORAGE...
According to at least some example embodiments of the inventive concepts, an electronic device includes an embedded storage device that is, configured to...
2018/0089115 PERSISTENT MEMORY WRITE SEMANTICS ON PCIE WITH EXISTING TLP DEFINITION
Aspects of the disclosure are directed to systems, methods, and devices that include an application processor. The application processor includes an interface...
2018/0089114 CUT-THROUGH BUFFER WITH VARIABLE FREQUENCIES
A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a...
2018/0089113 SYSTEM AND METHOD FOR INDIVIDUAL ADDRESSING
In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a...
2018/0089112 METHOD FOR SETTING UNIVERSAL SERIAL BUS (USB) INTERFACE OF ELECTRONIC DEVICE, AND ELECTRONIC DEVICE
Certain aspects of the disclosure relates to a method for operating an electronic device. A control device detects a Universal Serial Bus (USB) interface being...
2018/0089111 DISPLAY APPARATUS, DISPLAY CONTROL METHOD, AND COMPUTER READABLE RECORDING MEDIUM
A display apparatus including a display that displays messages includes a message retrieval unit that retrieves messages by accessing a message management...
2018/0089110 Intents and Locks with Intent
A computing device requests access to an application object from a remote storage system in order to locally execute application functionality without hosting...
2018/0089109 COMPUTER-IMPLEMENTED METHOD AND A SYSTEM FOR ENCODING A HEAP APPLICATION MEMORY STATE USING SHADOW MEMORY
A computer-implemented method for encoding an application memory that a program, executed on a computer, has access to, using a shadow memory corresponding to...
2018/0089108 SECURE COMPUTING
Techniques and logic are presented for encrypting and decrypting applications and related data within a multi-processor system to prevent tampering. The...
2018/0089107 METHOD, APPARATUS, AND SYSTEM FOR CACHING DATA
The present disclosure provided a method, apparatus, and system for caching data. In an embodiment of the present disclosure, the method for caching data...
2018/0089106 METHOD AND APPARATUS FOR REPLACING DATA BLOCK IN CACHE
The invention discloses a method for replacing a data block in a cache, including: selecting, at a specified interval, an available way from available ways of...
2018/0089105 MEMORY OPTIMIZATION BY PHASE-DEPENDENT DATA RESIDENCY
Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time...
2018/0089104 DIRECT MEMORY ACCESS BETWEEN AN ACCELERATOR AND A PROCESSOR USING A COHERENCY ADAPTER
Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to...
2018/0089103 DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL IN AN EMULATOR ENVIRONMENT
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a...
2018/0089102 Translation Lookaside Buffer
Embodiments disclosed pertain to apparatuses, systems, and methods for Translation Lookaside Buffers (TLBs) that support visualization and multi-threading....
2018/0089101 COMPUTER PRODUCT, METHOD, AND SYSTEM TO PROVIDE A VIRTUAL TARGET TO VIRTUALIZE TARGET SYSTEM STORAGE RESOURCES...
Provided are a computer product, method, and system to virtualize target system storage resources as virtual target storage resources. Target storage resources...
2018/0089100 Using a Virtual to Virtual Address Table for Memory Compression
A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of...
2018/0089099 OFFLOAD DATA TRANSFER ENGINE FOR A BLOCK DATA TRANSFER INTERFACE
In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data...
2018/0089098 LOCAL AND REMOTE DUAL ADDRESS DECODING
Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more...
2018/0089097 IMPLEMENTING HARDWARE ACCELERATOR FOR STORAGE WRITE CACHE MANAGEMENT FOR MANAGING CACHE DESTAGE RATES AND...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit...
2018/0089095 FLUSHING PAGES FROM SOLID-STATE STORAGE DEVICE
Embodiments of the present disclosure relate to a method and device for flushing pages from a solid-state storage device. Specifically, the present disclosure...
2018/0089094 PRECISE INVALIDATION OF VIRTUALLY TAGGED CACHES
Systems and methods for precise invalidation of cache lines of a virtually indexed virtually tagged (VIVT) cache include associating, with each cache line of...
2018/0089093 IMPLEMENTING SELECTIVE CACHE INJECTION
A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into...
2018/0089092 METHOD AND DEVICE FOR MANAGING CACHES
Embodiments of the present disclosure generally relate to a method and device for managing caches. In particular, the method may include in response to...
2018/0089091 CACHE AND COMPRESSION INTEROPERABILITY IN A GRAPHICS PROCESSOR PIPELINE
Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage...
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