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Patent # Description
2018/0097010 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing...
2018/0097009 THREE-DIMENSIONAL MEMORY DEVICE HAVING DRAIN SELECT LEVEL ISOLATION STRUCTURE AND METHOD OF MAKING THEREOF
A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack...
2018/0097008 SEMICONDUCTOR DEVICE
Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region...
2018/0097007 SEMICONDUCTOR DEVICE
To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced...
2018/0097006 Semiconductor Memory Devices
A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately...
2018/0097005 Thyristor Volatile Random Access Memory and Methods of Manufacture
Memory cells are formed with vertical thyristors to create a volatile memory array. Power consumption in such arrays is reduced or controlled with various...
2018/0097004 SEMICONDUCTOR DEVICE COMPRISING A STANDARD CELL
Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard...
2018/0097003 WRAP-AROUND TRENCH CONTACT STRUCTURE AND METHODS OF FABRICATION
A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is...
2018/0097002 SEPARATE N AND P FIN ETCHING FOR REDUCED CMOS DEVICE LEAKAGE
A method for forming a semiconductor device includes blocking a first region of a wafer and forming a plurality of fins in a second region of the wafer. A...
2018/0097001 VERTICAL FIN RESISTOR DEVICES
Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET...
2018/0097000 METHOD AND STRUCTURE FOR IMPROVING VERTICAL TRANSISTOR
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed...
2018/0096999 SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF
A method for fabricating a semiconductor structure includes providing a substrate including a device region, an isolation region, and a transition region...
2018/0096998 COMPOSITE ISOLATION STRUCTURES FOR A FIN-TYPE FIELD EFFECT TRANSISTOR
Structures for the isolation of a fin-type field-effect transistor and methods of forming isolation for a fin-type field-effect transistor. A first dielectric...
2018/0096997 EPITAXIAL OXIDE FIN SEGMENTS TO PREVENT STRAINED SEMICONDUCTOR FIN END RELAXATION
A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein...
2018/0096996 METHOD AND STRUCTURE FOR IMPROVING VERTICAL TRANSISTOR
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed...
2018/0096995 FINFET STRUCTURE AND FABRICATING METHOD OF GATE STRUCTURE
A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon...
2018/0096994 VERTICAL FIN RESISTOR DEVICES
Semiconductor devices and methods are provided in which vertical fin resistor devices are integrally formed as part of a process flow for fabricating FinFET...
2018/0096993 ELECTRONIC DEVICE INCLUDING A CASCODE CIRCUIT HAVING PRINCIPAL DRIVE AND BYPASS TRANSISTORS
An electronic device can include a first transistor including a first gate electrode; and a second transistor including a second gate electrode. The first and...
2018/0096992 SHALLOW TRENCH ISOLATION RECESS PROCESS FLOW FOR VERTICAL FIELD EFFECT TRANSISTOR FABRICATION
A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with...
2018/0096991 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE
A semiconductor device includes an enhancement-mode first p-channel MISFET, an enhancement-mode second p-channel MISFET, a drain conductor electrically and...
2018/0096990 TRANSISTOR WITH IMPROVED AIR SPACER
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is...
2018/0096989 SHALLOW TRENCH ISOLATION RECESS PROCESS FLOW FOR VERTICAL FIELD EFFECT TRANSISTOR FABRICATION
A semiconductor device includes structures formed in first and second regions of a semiconductor substrate. The structures in the first region are spaced with...
2018/0096988 BONDED SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade...
2018/0096987 Protection Circuit for Integrated Circuit Die-Let After Scribe Cut
A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A...
2018/0096986 ESD PROTECTION DIODE AND ELECTRONIC DEVICE INCLUDING THE SAME
Provided are an ESD protection diode and an electronic device including the same. An ESD protection diode and an electronic device including the same according...
2018/0096985 Method of Manufacturing a Semiconductor Device
A method of manufacturing a semiconductor device includes forming an amorphous silicon layer over a first isolation layer. The method further includes...
2018/0096984 METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE
A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic...
2018/0096983 CROSS-DOMAIN ESD PROTECTION CIRCUIT
An ESD protection circuit includes: a first current path switch arranged in a parallel connection with a first circuit and turned off when a first node voltage...
2018/0096982 METHOD AND SYSTEM FOR PROVIDING A MAGNETIC CELL USABLE IN SPIN TRANSFER TORQUE APPLICATIONS AND INCLUDING A...
A magnetic cell and method for providing the magnetic cell are described. A magnetic cell resides on a substrate and is usable in a magnetic device. The...
2018/0096981 STANDARD CELL LAYOUT, SEMICONDUCTOR DEVICE HAVING ENGINEERING CHANGE ORDER (ECO) CELLS AND METHOD
A method of designing, for a semiconductor device, a layout which includes standard spare cells. Such a method includes: generating a set of possible values...
2018/0096980 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR MOUNTING DEVICE, AND MEMORY DEVICE MANUFACTURED BY...
A method for manufacturing a semiconductor device includes laminating a plurality of semiconductor wafers via an adhesive, heating such that the adhesive...
2018/0096979 A STACKED SEMICONDUCTOR PACKAGE HAVING FAULT DETECTION AND A METHOD FOR IDENTIFYING A FAULT IN A STACKED PACKAGE
A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory...
2018/0096978 Photo-Sensitive Silicon Package Embedding Self-Powered Electronic System
A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline...
2018/0096977 APPARATUS FOR MICRO PICK AND BOND
Embodiments of the invention include systems and methods for transferring micro LEDs. In an embodiment, the system for transferring micro LEDs, may include a...
2018/0096976 Solution for Reducing Poor Contact in InFO Package
A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding...
2018/0096975 HIGH DENSITY PACKAGE ON PACKAGE DEVICES CREATED THROUGH A SELF ASSEMBLY MONOLAYER ASSISTED LASER DIRECT...
A high density package on package electrical device is disclosed. The electrical device comprises a first integrated circuit package comprising a substrate, an...
2018/0096974 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package includes a semiconductor chip, an interposer, a first redistribution layer, and a molding compound. The semiconductor chip has a first...
2018/0096973 System and Method for Providing 3D Wafer Assembly With Known-Good-Dies
Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and...
2018/0096972 WAFER LEVEL PACKAGE AND WAFER LEVEL CHIP SIZE PACKAGE
A wafer level package that includes a first wafer; a second wafer facing the first wafer; a plurality of chips between the first wafer and the second wafer and...
2018/0096971 SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN TWO-LEVEL MEMORY (2LM) STACKED DIE SUBSYSTEMS
In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked...
2018/0096970 INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE
A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one...
2018/0096969 METHOD OF PRODUCING AN INTERPOSER-CHIP-ARRANGEMENT FOR DENSE PACKAGING OF CHIPS
The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2)...
2018/0096968 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component...
2018/0096967 ELECTRONIC PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
An electronic package structure is provided, which includes: a plurality of first and second electronic components disposed on opposite sides of a carrier; a...
2018/0096966 Multi-Purpose Non-Linear Semiconductor Package Assembly Line
A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The...
2018/0096965 METHOD FOR FORMING BALL IN BONDING WIRE
The present invention provides a ball forming method for forming a ball portion at a tip of a bonding wire which includes a core material mainly composed of...
2018/0096964 MICRO-TRANSFER PRINTING WITH VOLATILE ADHESIVE LAYER
A method of making a micro-transfer printed structure includes providing a destination substrate and a source substrate having one or more micro-transfer...
2018/0096962 SUBSTRATE ATTACHMENT FOR ATTACHING A SUBSTRATE THERETO
A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the...
2018/0096961 SEMICONDUCTOR DEVICE
To improve a performance of a semiconductor device, a semiconductor device includes a lead electrically coupled to a semiconductor chip via a wire. An inner...
2018/0096960 Tall and Fine Pitch Interconnects
Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board...
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