Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0096909 SEMICONDUCTOR DEVICE HAVING TWO ENCAPSULANTS
A semiconductor device includes a substrate, a semiconductor die mounted on and electrically connected to the substrate, and first and second encapsulants that...
2018/0096908 SEMICONDUCTOR DEVICE
The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse...
2018/0096907 SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME
A method for forming semiconductor packages includes disposing at least one flow hindering supporter onto a substrate, in which the substrate has at least one...
2018/0096906 System and Method for Process-Induced Distortion Prediction During Wafer Deposition
A system is disclosed. The system includes a tool cluster. The tool cluster includes a first deposition tool configured to deposit a first layer on a wafer....
2018/0096905 FACILITATION OF SPIN-COAT PLANARIZATION OVER FEATURE TOPOGRAPHY DURING SUBSTRATE FABRICATION
Described herein are technologies to facilitate device fabrication, especially those that involve spin-on coatings of a substrate (e.g., wafer). More...
2018/0096904 CAPACITANCE MONITORING USING X-RAY DIFFRACTION
A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak...
2018/0096903 FAN-OUT PANEL LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME
A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with...
2018/0096902 METALIZATION REPAIR IN SEMICONDUCTOR WAFERS
Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor...
2018/0096901 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2018/0096900 INTEGRATED CIRCUIT WITH REPLACEMENT GATE STACKS AND METHOD OF FORMING SAME
A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an...
2018/0096899 METHOD OF MANUFACTURING SELECTIVE NANOSTRUCTURES INTO FINFET PROCESS FLOW
A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and...
2018/0096898 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION
A method of semiconductor device fabrication includes providing a substrate including a first fin element and a second fin element extending from the...
2018/0096897 METHOD OF FABRICATING DMOS AND CMOS TRANSISTORS
A method of fabricating a semiconductor device including a diffused metal-oxide-semiconductor (DMOS) transistor, an n-type metal-oxide-semiconductor (NMOS)...
2018/0096896 SEMICONDUCTOR ARRANGEMENT, METHOD OF MANUFACTURING THE SAME ELECTRONIC DEVICE INCLUDING THE SAME
There are provided a semiconductor arrangement, a method of manufacturing the same, and an electronic device including the semiconductor arrangement. According...
2018/0096895 PREVENTING OXIDATION DEFECTS IN STRAIN-RELAXED FINS BY REDUCING LOCAL GAP FILL VOIDS
A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom...
2018/0096894 METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR DEVICE STRUCTURE
The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric...
2018/0096893 CONTACT RESISTANCE REDUCTION BY III-V Ga DEFICIENT SURFACE
A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate....
2018/0096892 DEVICE WAFER PROCESSING METHOD
A device wafer processing method includes forming a mask patterned so as to cover plural devices formed on a front side of the wafer and expose streets between...
2018/0096891 SELF-ALIGNED CONTACTS
A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate...
2018/0096890 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second...
2018/0096889 MANUFACTURING METHOD OF INTERCONNECTION STRUCTURE
An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first...
2018/0096888 DOPED SELECTIVE METAL CAPS TO IMPROVE COPPER ELECTROMIGRATION WITH RUTHENIUM LINER
Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method...
2018/0096887 VIA AND CHAMFER CONTROL FOR ADVANCED INTERCONNECTS
Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is...
2018/0096886 COMPOSITE DIELECTRIC INTERFACE LAYERS FOR INTERCONNECT STRUCTURES
Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm.sup.3 are deposited...
2018/0096885 SELF-ALIGNED TRENCH METAL-ALLOYING FOR III-V NFETS
After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces...
2018/0096884 LOCAL TRAP-RICH ISOLATION
A trap-rich polysilicon layer is interposed between the active (SOI) layer and the underlying handle portion of a semiconductor substrate to prevent or...
2018/0096883 FABRICATION OF SILICON GERMANIUM-ON-INSULATOR FINFET
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe...
2018/0096882 Isolated Semiconductor Layer Over Buried Isolation Layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
2018/0096881 MULTIPLE FINFET FORMATION WITH EPITAXY SEPARATION
A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX)...
2018/0096880 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within...
2018/0096879 SPIN CHUCK INCLUDING EDGE RING
Apparatus for treating a substrate includes a stationary plate assembly including liquid nozzles to direct liquid at an edge of the substrate during treatment....
2018/0096878 VACUUM SUCTION APPARATUS
A vacuum suction apparatus includes a semiconductor substrate with a top portion having grooves and a bottom portion having through holes, wherein each said...
2018/0096877 MULTI-CHIP PACKAGE ASSEMBLY
Methods of bonding chips to a substrate and transfer wafers used for such bonding include bonding chips to a first support wafer by a first adhesive layer. The...
2018/0096876 Support Apparatus and Support Method
A support apparatus and a support method are provided, the support apparatus includes: a support substrate for bearing a supported component, the support...
2018/0096875 ADJUSTABLE CIRCUMFERENCE ELECTROSTATIC CLAMP
An electrostatic chuck for clamping workpieces having differing diameters is provided. A central electrostatic chuck member associated with a first workpiece...
2018/0096874 DYNAMIC LEVELING PROCESS HEATER LIFT
A method and apparatus for of improving processing results in a processing chamber by orienting a substrate support relative to a surface within the processing...
2018/0096873 INTEGRATED SYSTEMS FOR INTERFACING WITH SUBSTRATE CONTAINER STORAGE SYSTEMS
A storage system and methods for operating a storage system are disclosed. The storage system includes a plurality of storage shelves, and each of storage...
2018/0096872 3D IC BUMP HEIGHT METROLOGY APC
In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a...
2018/0096871 Methods and Apparatus to Prevent Interference Between Processing Chambers
Methods and apparatus to minimize electromagnetic interference between adjacent process chambers of a cluster tool are described. The start time of the subject...
2018/0096870 ELECTROSTATIC CHUCK AND SUBSTRATE FIXING DEVICE
An electrostatic chuck includes a heating part, a substrate on the heating part, a temperature sensor, and an embedment part. The substrate includes a first...
2018/0096869 ELECTROSTATIC CHUCK AND SUBSTRATE FIXING DEVICE
An electrostatic chuck includes a heating part, a substrate on the heating part, a temperature sensor, and a metal material. The substrate includes a first...
2018/0096868 CERAMIC HEATER
The ceramic heater includes: a ceramic base body made of ceramic and having an upper surface on which an object to be heated is to be placed; a heating...
2018/0096866 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus includes processing parts performing substrate processing on target substrates, respectively, substrate mounting tables...
2018/0096865 OXYGEN COMPATIBLE PLASMA SOURCE
Described processing chambers may include a chamber housing at least partially defining an interior region of a semiconductor processing chamber. The chamber...
2018/0096864 SUBSTRATE PROCESSING APPARATUS
According to one embodiment, a substrate processing apparatus includes a processing chamber, a support part, a heater, and an optical member. In the processing...
2018/0096863 SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS, AND STORAGE MEDIUM
Disclosed is a substrate liquid processing method including: a first processing step of discharging a fluid in the processing container until an inside of the...
2018/0096862 COMPLEX CAVITY FORMATION IN MOLDED PACKAGING STRUCTURES
Molded electronics package cavities are formed by placing a sacrificial material in the mold and then decomposing, washing, or etching away this sacrificial...
2018/0096861 METHOD OF MACHINING A LEAD FRAME, AND LEAD FRAME
A method of processing a lead frame having at least one electrically conductive contact section includes forming a depression in the at least one electrically...
2018/0096860 Leadframe Having Organic, Polymerizable Photo-Imageable Adhesion Layer
A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a...
2018/0096859 PROCESS FOR FORMING LEADFRAME HAVING ORGANIC, POLYMERIZABLE PHOTO-IMAGEABLE ADHESION LAYER
A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.