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Patent # Description
2018/0102354 METHOD, APPARATUS, AND SYSTEM FOR TWO-DIMENSIONAL POWER RAIL TO ENABLE SCALING OF A STANDARD CELL
At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination...
2018/0102353 ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS
An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on...
2018/0102352 Fluid-Suspended Microcomponent Harvest, Distribution, and Reclamation
Fluid-suspended microcomponent management systems and methods are provided. The method provides a first reservoir containing a first solution and a magnetic...
2018/0102351 Semiconductor Devices and Methods of Manufacture Thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip...
2018/0102350 LED DISPLAY MODULES AND METHODS FOR MAKING THE SAME
An LED display module is disclosed. The LED display module includes: an active matrix substrate including a plurality of control units; a plurality of pairs of...
2018/0102349 MULTI-PHASE POWER CONVERTER WITH COMMON CONNECTIONS
In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises...
2018/0102348 OPTOELECTRONIC COMPONENT AND METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT
An optoelectronic component includes a carrier, wherein a first optoelectronic semiconductor chip and a second optoelectronic semiconductor chip are arranged...
2018/0102347 DATA STORAGE DEVICE HAVING MULTI-STACK CHIP PACKAGE AND OPERATING METHOD THEREOF
Disclosed is a data storage device including a controller and a multi-stack chip package, and a method of operating a data storage device. The multi-stack chip...
2018/0102346 SEMICONDUCTOR DEVICE
In a semiconductor device, a first semiconductor chip having a main surface provided with a first terminal group including terminals, and a rear face mounted...
2018/0102345 Semiconductor Device and Method of Manufacture
An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the...
2018/0102344 NON-VOLATILE MEMORY SYSTEM WITH WIDE I/O MEMORY DIE
A non-volatile storage system includes a plurality of memory dies and an interface circuit. Each memory die includes a wide I/O interface electrically coupled...
2018/0102343 SEMICONDUCTOR PACKAGE WITH IMPROVED BANDWIDTH
A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a...
2018/0102342 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
2018/0102341 Conductive Paste For Bonding
The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal...
2018/0102340 APPARATUS FOR CORRECTING A PARALLELISM BETWEEN A BONDING HEAD AND A STAGE, AND A CHIP BONDER INCLUDING THE SAME
A bonding apparatus includes a detecting unit configured to determine whether a bonding head and a stage, on which a package substrate is disposed, are...
2018/0102339 SEMICONDUCTOR PACKAGE
A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor...
2018/0102338 CIRCUIT BOARD WITH BRIDGE CHIPLETS
Various circuit boards and methods of fabricating and using the same are disclosed. In one aspect, a system is provided that has a circuit board with a pocket...
2018/0102337 CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT
A method of fabricating a pillar-type connection includes forming a second conductive layer on a first conductive layer to define a conductive pillar that...
2018/0102336 MIXED UBM AND MIXED PITCH ON A SINGLE DIE
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
2018/0102335 MIXED UBM AND MIXED PITCH ON A SINGLE DIE
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and...
2018/0102334 WAFER LAMINATE AND METHOD OF PRODUCING THE SAME
To provide a wafer laminate which permits easy bonding between a support and a wafer, permits easy delamination of a wafer from a support, enables enhanced...
2018/0102333 WAFER LAMINATE, METHOD FOR PRODUCTION THEREOF, AND ADHESIVE COMPOSITION FOR WAFER LAMINATE
Disclosed herein is a wafer laminate suitable for production of thin wafers and a method for producing the wafer laminate. The wafer laminate can be formed...
2018/0102332 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip...
2018/0102331 Interconnections for a Substrate Associated with a Backside Reveal
An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An...
2018/0102330 SENSING CHIP PACKAGE HAVING ESD PROTECTION AND METHOD MAKING THE SAME
A chip package having ESD protection and a method for making the chip are disclosed. The chip package includes a chip and a substrate. The chip includes a...
2018/0102329 TAMPER-PROOF ELECTRONIC PACKAGES WITH STRESSED GLASS COMPONENT SUBSTRATE(S)
Tamper-proof electronic packages and fabrication methods are provided which include a glass substrate. The glass substrate is stressed glass with a...
2018/0102328 INTEGRATED CIRCUIT CHIP REINFORCED AGAINST FRONT SIDE DEPROCESSING ATTACKS
An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the...
2018/0102327 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the...
2018/0102326 Perimeter Control Of Crack Propagation In Semiconductor Wafers
A semiconductor substrate such as a wafer includes a scoring that is inset from the perimeter. The scoring follows the perimeter or a portion thereof. The...
2018/0102325 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device includes a substrate, a die, a package body, a shielding layer, a solder mask layer, an insulating film and an interconnection...
2018/0102324 MARK FORMING METHOD AND DEVICE MANUFACTURING METHOD
A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is...
2018/0102323 ARRANGEMENT FOR SPATIALLY LIMITING A RESERVOIR FOR A MARKER MATERIAL
An arrangement includes a confining layer, a metallization layer and a semiconductor component, wherein the metallization layer is arranged on the...
2018/0102322 FAN-OUT SEMICONDUCTOR PACKAGE
The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend...
2018/0102321 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The...
2018/0102320 SELF-FORMED LINER FOR INTERCONNECT STRUCTURES
An interconnect dielectric material having an opening formed therein is first provided. A surface nitridation process is then performed to form a nitridized...
2018/0102319 Methods for Reducing Dual Damascene Distortion
An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value...
2018/0102318 COMPOUND RESISTOR STRUCTURE FOR SEMICONDUCTOR DEVICE
A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a...
2018/0102317 INTERCONNECT STRUCTURES WITH FULLY ALIGNED VIAS
A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a...
2018/0102316 INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that...
2018/0102315 SURFACE AREA-DEPENDENT SEMICONDUCTOR DEVICE WITH INCREASED SURFACE AREA
The surface area of a surface area-dependent semiconductor device is increased by providing a dielectric layer, removing portion(s) of the dielectric layer,...
2018/0102314 SEMICONDUCTOR DEVICE
A semiconductor device may be provided. The semiconductor device may include conductive patterns surrounding a channel film. The conductive patterns may be...
2018/0102313 WAFER LEVEL PACKAGE UTILIZING MOLDED INTERPOSER
A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer...
2018/0102312 Fabrication Process and Structure of Fine Pitch Traces for a Solid State Diffusion Bond on Flip Chip Interconnect
A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a...
2018/0102311 SEMICONDUCTOR PACKAGE UTILIZING EMBEDDED BRIDGE THROUGH-SILICON-VIA INTERCONNECT COMPONENT
A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a...
2018/0102310 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of...
2018/0102309 POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located...
2018/0102308 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE
In some embodiments, a semiconductor device includes a semiconductor chip including a first terminal, a second terminal and a third terminal, a frame...
2018/0102307 COMMON CONTACT LEADFRAME FOR MULTIPHASE APPLICATIONS
In some examples, a device includes an input leadframe segment and a reference leadframe segment that is electrically isolated from the input leadframe...
2018/0102306 MULTI-PHASE COMMON CONTACT PACKAGE
In some examples, a device includes a first leadframe segment and a second leadframe segment, wherein the second leadframe segment is electrically isolated...
2018/0102305 SEMICONDUCTOR DEVICE AND LEAD FRAME WITH HIGH DENSITY LEAD ARRAY
A semiconductor device includes a lead frame having leads arranged in an array that has columns extending in a first direction and rows extending in a second...
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