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Patent # Description
2018/0102202 CONDUCTIVE PATH
A conductive path includes: a first conductor in which a terminal end portion serves as a first connection portion; a second conductor in which a second...
2018/0102201 STRETCHABLE CONDUCTIVE FIBER AND METHOD OF MANUFACTURING THE SAME
Disclosed are a conductive fiber and a method of manufacturing the same. More particularly, the conductive fiber according to the present disclosure includes...
2018/0102200 Laser-based Fabrication of Carbon Nanotube-Metal Composites on Flexible Substrates
The present disclosure relates to a novel method of laser-based fabrication of a carbon nanotube (CNT)-metal composite on a flexible substrate, and the...
2018/0102199 COPPER ALLOY WIRE, COPPER ALLOY TWISTED WIRE, COVERED ELECTRIC WIRE, AND WIRING HARNESS
A copper alloy wire, a copper alloy twisted wire, a covered electric wire, and a wiring harness that have high strength and excellent impact resistance. A...
2018/0102198 CONDUCTIVE PASTE COMPOSITION AND SEMICONDUCTOR DEVICES MADE THEREWITH
The present invention provides a thick-film paste composition for printing the front side of a solar cell device having one or more insulating layers. The...
2018/0102197 Graphene-Copper Composite Structure and Manufacturing Method
A composite structure comprises a copper layer and first and second graphene layers sandwiching the copper layer, wherein the composite structure provides...
2018/0102196 PRODUCTION OF MOLYBDENUM-99 USING ELECTRON BEAMS
An apparatus for producing .sup.99Mo from a plurality of .sup.100Mo targets through a photo-nuclear reaction on the .sup.m.degree. Mo targets. The apparatus...
2018/0102195 CHARGE STRIPPING FILM FOR CHARGE STRIPPING DEVICE OF ION BEAM
A charge stripping film for a charge stripping device of ion beam is a carbon film produced by annealing a polymer film, and has a film thickness of 10 .mu.m...
2018/0102194 DECONTAMINATION METHOD REDUCING RADIOACTIVE WASTE REMARKABLY AND A KIT THEREFOR
The present invention provides a decontamination method including the steps of decontaminating an object containing radioactive contaminated metals or alloys...
2018/0102193 INSTALLATION STRUCTURE FOR INSTALLING CONTROL ROD DRIVE MECHANISM AND CABLE SEALING UNIT IN NUCLEAR REACTOR...
Provided is an installation structure for installing control rod drive mechanisms and cable sealing units in a nuclear reactor pressure vessel. The...
2018/0102192 RESISTANCE PRESSURE WELD FOR NUCLEAR REACTOR FUEL ROD TUBE END PLUG
A fuel rod for a nuclear reactor, including a cladding tube having a first end with an annular end face, a second end with an annular end face, and a...
2018/0102191 CYCLIC NUCLEAR FUSION WITH SINGLE-CYCLE, CHARGED CATHODE
A controlled fusion process is provided that can produce a sustained series of fusion reactions: a process that (i) uses a substantially higher reactant...
2018/0102190 GENERATING CUSTOMIZABLE PERSONAL HEALTHCARE TREATMENT PLANS
Personalized treatment plan generation from an inference engine of a system. The system may receive or retrieve data from a plurality of sources and parse the...
2018/0102189 ENDOSCOPIC EXAMINATION WORK SUPPORT SYSTEM
An examination schedule management unit manages an examination schedule of a plurality of endoscopic examinations, including an examination room where an...
2018/0102188 METHOD FOR ASSISTING PATIENTS IN NAVIGATING A HEALTHCARE NETWORK FROM PRE-PROCEDURE THROUGH POST-ADMISSION
In an embodiment, a first communication that is an electronic hospital census and/or an outpatient authorization report is received by a control device...
2018/0102187 METHOD AND SYSTEM FOR CHARACTERIZING A HEADACHE-RELATED CONDITION
Embodiments of a method and/or system for characterizing a headache-related condition for a user can include one or more of: generating a microbiome dataset...
2018/0102186 METHOD AND SYSTEM FOR MANAGING ELECTRONIC INFORMED CONSENT PROCESS IN CLINICAL TRIALS
A method and a system for managing an electronic informed consent process in a clinical trial are provided. The method includes tracking time spent by a...
2018/0102185 FUSE CIRCUIT, REPAIR CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME
A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect...
2018/0102184 Screening for Data Retention Loss in Ferroelectric Memories
A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM...
2018/0102183 METHODS OF TESTING CELL ARRAYS AND SEMICONDUCTOR DEVICES EXECUTING THE SAME
A semiconductor device includes a pattern data generation circuit generating pattern data, a data comparison circuit receiving read data which are outputted...
2018/0102182 METHODS FOR TESTING A STORAGE UNIT AND APPARATUSES USING THE SAME
The invention introduces a method for testing a storage unit, performed by a processing unit, including at least the following steps: after receiving a test...
2018/0102181 MEMORY CIRCUIT WITH ASSIST CIRCUIT TRIMMING
A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional,...
2018/0102180 High Voltage Bootstrap Sampling Circuit
A bootstrapped sampling switch may be used at lower supply voltages due to its high linearity, wherein the sampled voltage may be substantially higher than the...
2018/0102179 ONE TIME PROGRAMMABLE READ-ONLY MEMORY (ROM) IN SOI CMOS
A method of operating a programmable read-only-memory (ROM) cell unit having a series coupled CMOS NFET and CMOS PFET device formed on a semiconductor layer...
2018/0102178 MULTI-TIME PROGRAMMABLE DEVICE
Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions...
2018/0102177 3D MEMORY WITH STAGED-LEVEL MULTIBIT PROGRAMMING
A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of...
2018/0102176 DELAYING PROGRAMMING REQUESTS IN FLASH MEMORY
Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead...
2018/0102175 POWER SUPPLY CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
A power supply circuit and a semiconductor storage device that can achieve low power consumption of the power supply circuit that includes a charge pump...
2018/0102174 CONTROL VOLTAGE SEARCHING METHOD FOR NON-VOLATILE MEMORY
A control voltage searching method is provided. Firstly, a control pulse with a preset control voltage and a preset pulse width is generated, and a control...
2018/0102173 Buffered Automated Flash Controller Connected Directly to Processor Memory Bus
A mechanism is provided for buffer linking in a buffered solid state drive controller. Responsive to the buffered flash memory module receiving from a memory...
2018/0102172 MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
A memory device includes a memory cell array including a plurality of blocks, a power supply unit suitable for generating at least one erase voltage and...
2018/0102171 RRAM ARRAY WITH CURRENT LIMITING ELEMENT
In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) circuit. The RRAM circuit has a plurality of RRAM cells. A...
2018/0102170 METHOD, SYSTEM AND DEVICE FOR POWER-UP OPERATION
Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one...
2018/0102169 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a nonvolatile memory device including a reference memory region and a normal memory region, and suitable for determining whether...
2018/0102168 MAPPING BITS TO MEMORY CELLS USING SECTOR SPREADING
A method for storing data multi-level cell (MLC) memory includes receiving data to be stored. The received data is divided into units of x bits, where x is an...
2018/0102167 METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE AND A METHOD FOR OPERATING A SYSTEM HAVING THE SAME
A method for programming a non-volatile memory device includes programming a lower bit in a memory cell included in the non-volatile memory device, reading the...
2018/0102165 SRAM MODULE AND WRITING CONTROL METHOD THEREOF
A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that...
2018/0102164 MEMORY DEVICE SENSING CIRCUIT
A memory device includes a first memory array comprising a first bit cell configured to store a first logical state; and a reference signal provision (RSP)...
2018/0102163 SRAM-BASED AUTHENTICATION CIRCUIT
A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data...
2018/0102162 RECONFIGURABLE CLOCKING ARCHITECTURE
Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit...
2018/0102161 Vertical Thyristor Memory Array and Memory Array Tile Therefor
In a vertical thyristor memory cell array with each of the thyristor memory cells connected to bit and word lines, the bit lines are connected to the inputs of...
2018/0102160 DDR Controller for Thyristor Memory Cell Arrays
A vertical thyristor memory cell array with each of the thyristor memory cells connected to bit and word lines, the bit lines are connected to the inputs of...
2018/0102159 MEMORY DISTURB RECOVERY SCHEME FOR CROSS-POINT MEMORY ARRAYS
Methods and systems are described herein for determining if bit cell read or write rates require a refresh of the accessed or neighboring bit cells. The...
2018/0102158 REPROGRAMMABLE NON-VOLATILE FERROELECTRIC LATCH FOR USE WITH A MEMORY CONTROLLER
Methods, systems, and apparatuses related to a reprogrammable non-volatile latch are described. A latch may include ferroelectric cells, ferroelectric...
2018/0102157 COMPENSATING FOR VARIATIONS IN SELECTOR THRESHOLD VOLTAGES
Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of...
2018/0102156 RESISTANCE CHANGE MEMORY
According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a...
2018/0102155 PUF CIRCUIT AND MAGNETORESISTIVE DEVICE AND CONTROL METHOD THEREOF
A physically-unclonable-function (PUF) circuit and the control method thereof are provided, and the control method can be applied to the magnetoresistive...
2018/0102154 ELECTRONIC DEVICE
In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance...
2018/0102153 SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT
Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in...
2018/0102152 METHODS FOR ADDRESSING HIGH CAPACITY SDRAM-LIKE MEMORY WITHOUT INCREASING PIN COST
A method for addressing memory device data arranged in rows and columns indexed by a first number of row address bits and a second number of column address...
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