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Patent # Description
2018/0108655 PRESERVING CHANNEL STRAIN IN FIN CUTS
A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET...
2018/0108654 FINFET DEVICE WITH LOW RESISTANCE FINS
A method of forming a FinFET device includes ion implanting a diffusion-inhibiting species such as carbon into source and drain regions of a semiconductor fin...
2018/0108653 SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate,...
2018/0108652 SWITCH CIRCUIT WITH CONTROLLABLE PHASE NODE RINGING
A switch circuit includes a first MOS transistor and a second MOS transistor of a same conductivity type connected in parallel between a first terminal and a...
2018/0108651 DEEP TRENCH METAL-INSULATOR-METAL CAPACITORS
Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level...
2018/0108650 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING AN ESD PROTECTION CIRCUIT
Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring...
2018/0108649 ARRAY SUBSTRATE AND DISPLAY DEVICE
An array substrate and a display device are provided. The array substrate includes a display region and a peripheral region surrounding the display region....
2018/0108648 Electrostatic Discharge Protection Structure, Method for Manufacturing an Electrostatic Discharge Protection...
According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first...
2018/0108647 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first...
2018/0108646 INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and...
2018/0108644 METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES
A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier...
2018/0108643 DRIVING CHIP BUMP HAVING IRREGULAR SURFACE PROFILE, DISPLAY PANEL CONNECTED THERETO AND DISPLAY DEVICE...
A display device includes: a display panel driven to display an image, the display panel including a substrate including a display area at which the image is...
2018/0108642 INTERPOSER HEATER FOR HIGH BANDWIDTH MEMORY APPLICATIONS
A method for integrating heaters in high bandwidth memory (HBM) applications and the related devices are provided. Embodiments include forming a silicon (Si)...
2018/0108641 HIGH FREQUENCY INTEGRATED CIRCUIT AND EMITTING DEVICE FOR IRRADIATING THE INTEGRATED CIRCUIT
What is described is a high-frequency integrated circuit provided on a III-V compound semiconductor, wherein an emitting device is radiation-coupled with the...
2018/0108640 DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A display device includes a substrate having flexibility, a first surface and a second surface opposing the first surface, a display part arranged with a...
2018/0108639 METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a...
2018/0108638 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact...
2018/0108637 Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices
Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device...
2018/0108636 FLEXIBLE DISPLAY PANEL, DISPLAY DEVICE AND BONDING METHOD THEREOF
A flexible display panel, a display device and a bonding method thereof are provided. The flexible display panel includes a plurality of fan-out leads arranged...
2018/0108635 CONNECTING TECHNIQUES FOR STACKED CMOS DEVICES
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a semiconductor substrate, and an inter-tier...
2018/0108634 SEMICONDUCTOR PACKAGE, INTERPOSER AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME
A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first main body, at...
2018/0108633 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The...
2018/0108632 SOLDER BUMP STRETCHING METHOD
A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein...
2018/0108631 FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER
Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal...
2018/0108630 FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER
Wafers include multiple bulk redistribution layers. A terminal contact pad is on a surface of one of the bulk redistribution layers. A final redistribution...
2018/0108629 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To improve the reliability of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on a semiconductor substrate, a pad...
2018/0108628 CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE
A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate...
2018/0108627 CIRCUIT DEVICE, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT
A circuit device includes a first pad and a second pad that are disposed in a first pad disposition region along a first side; a third pad and a fourth pad...
2018/0108626 FINAL PASSIVATION FOR WAFER LEVEL WARPAGE AND ULK STRESS REDUCTION
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An...
2018/0108625 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring that is provided on a first surface of the...
2018/0108624 SEMICONDUCTOR PACKAGE WITH THREE-DIMENSIONAL ANTENNA
A semiconductor package is provided. The semiconductor package includes a package substrate having a first region and a second region defined between an edge...
2018/0108623 ELECTRONIC DEVICE WITH MICROFILM ANTENNA AND RELATED METHODS
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
2018/0108622 RF Module
In accordance with an embodiment, an RF module includes a bulk semiconductor substrate with at least one integrated RF component integrated in a first main...
2018/0108621 RESONANCE-COUPLED SIGNALING BETWEEN IC MODULES
Coupled resonators for galvanically isolated signaling between integrated circuit modules. An illustrative multi-module integrated circuit comprises: a...
2018/0108620 CAVITY FORMATION IN BACKSIDE INTERFACE LAYER FOR RADIO-FREQUENCY ISOLATION
A semiconductor device includes a transistor device implemented over an oxide layer, an interface layer applied below at least a portion of the oxide layer,...
2018/0108619 SUBSTRATE STRUCTURE, PACKAGING METHOD AND SEMICONDUCTOR PACKAGE STRUCTURE
A substrate structure includes a substrate body, at least one first mold area and at least one second mold area. The substrate body has a first surface and a...
2018/0108618 MODULE AND METHOD FOR MANUFACTURING SAME
A module includes a wiring board, a plurality of components mounted on an upper surface of the wiring board, a sealing resin layer which seals the components...
2018/0108617 ELECTRONIC CIRCUIT PACKAGE USING COMPOSITE MAGNETIC SEALING MATERIAL
Disclosed herein is an electronic circuit package includes a substrate, an electronic component mounted on a surface of the substrate, and a magnetic mold...
2018/0108616 DEVICE HAVING SUBSTRATE WITH CONDUCTIVE PILLARS
A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up...
2018/0108615 PACKAGE STRUCTURE AND ITS FABRICATION METHOD
This disclosure provides a package structure and its fabrication method. The package structure includes: a conductive pattern layer having a bump region and a...
2018/0108614 STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection...
2018/0108613 STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT STRUCTURE
Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a...
2018/0108612 Embedded Vialess Bridges
Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are...
2018/0108611 SPLIT RAIL STRUCTURES LOCATED IN ADJACENT METAL LAYERS
A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that...
2018/0108610 LINER PLANARIZATION-FREE PROCESS FLOW FOR FABRICATING METALLIC INTERCONNECT STRUCTURES
A method includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening in the dielectric layer. A first layer of...
2018/0108609 SENSOR DEVICE
A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect...
2018/0108608 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
The invention provides a memory device. The memory device includes a substrate, a plurality of first wires, a plurality of etch-stop layers, a dielectric...
2018/0108607 IC STRUCTURE INCLUDING TSV HAVING METAL RESISTANT TO HIGH TEMPERATURES AND METHOD OF FORMING SAME
An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a...
2018/0108606 FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE
A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads,...
2018/0108605 LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
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