Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0114774 Semiconductor Package
A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second...
2018/0114773 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked...
2018/0114772 METHOD FOR SIMULTANEOUSLY BONDING MULTIPLE CHIPS OF DIFFERENT HEIGHTS ON FLEXIBLE SUBSTRATES USING ANISOTROPIC...
The present application provides methods, systems and devices for simultaneously bonding multiple semiconductor chips of different height profiles on a...
2018/0114771 METHOD OF DETERMINING CURING CONDITIONS, METHOD OF PRODUCING CIRCUIT DEVICE, AND CIRCUIT DEVICE
A method of determining curing conditions is for determining the curing conditions of a thermosetting resin to seal a conductive part between a substrate and...
2018/0114770 Substrateless Integrated Circuit Packages and Methods of Forming Same
Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are...
2018/0114769 Chip Packaging Structure and Related Inner Lead Bonding Method
A chip packaging structure includes a chip and a film substrate. The chip is formed with a gold bump, and the film substrate is formed with an inner lead,...
2018/0114768 SEMICONDUCTOR CHIP, ELECTRONIC DEVICE HAVING THE SAME AND METHOD OF CONNECTING SEMICONDUCTOR CHIP TO ELECTRONIC...
Provided herein may be an electronic device. The electronic device may include a substrate provided with a plurality of connecting pads including a first...
2018/0114767 BOND HEAD ASSEMBLIES INCLUDING REFLECTIVE OPTICAL ELEMENTS, RELATED BONDING MACHINES, AND RELATED METHODS
A bond head assembly for a bonding machine is provided. The bond head assembly includes a body portion and a bonding tool for bonding a semiconductor element...
2018/0114766 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present invention includes: preparing a semiconductor substrate having a first main surface and a second main surface that is located on an opposite side...
2018/0114765 SEMICONDUCTOR DEVICE
An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal...
2018/0114764 METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate; a pad disposed over the...
2018/0114763 METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE
The present disclosure provides a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate having a first surface...
2018/0114762 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element...
2018/0114761 PRE-CONDITIONED SELF-DESTRUCTING SUBSTRATE
A self-destructing device includes a frangible substrate having at least one pre-weakened area. A heater is thermally coupled to the frangible substrate...
2018/0114760 Package Substrate and Fabrication Method Thereof, and Integrated Circuit Chip
A package substrate, including a first reference layer and a second reference layer disposed opposite to each other, a first composite layer disposed on a side...
2018/0114759 ELECTRONIC COMPONENT MODULE AND MANUFACTURING METHOD THEREOF
Disclosed herein is an electronic component module that includes, an electronic component, a mold resin that seals the electronic component, a conductive film...
2018/0114758 SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device package comprises a substrate, a first electronic component, first and second conductive pads, a first frame board, an encapsulation...
2018/0114757 SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the...
2018/0114756 DEVICE AND METHOD FOR ALIGNMENT OF VERTICALLY STACKED WAFERS AND DIE
A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern...
2018/0114755 SEMICONDUCTOR DEVICE
In a semiconductor device, a plurality of first wirings (X-direction) include a first power supply line and a second power supply line, a plurality of third...
2018/0114754 METHOD FOR PROVIDING ELECTRICAL ANTIFUSE INCLUDING PHASE CHANGE MATERIAL
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
2018/0114753 SEMICONDUCTOR CHIP AND MULTI-CHIP PACKAGE USING THEREOF AND METHOD FOR MANUFACTURING THE SAME
The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip...
2018/0114752 SKIP-VIAS BYPASSING A METALLIZATION LEVEL AT MINIMUM PITCH
A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first...
2018/0114751 SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE LINES AND METHODS OF FORMING THE SEMICONDUCTOR DEVICES
A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged...
2018/0114750 SELECTIVE BLOCKING BOUNDARY PLACEMENT FOR CIRCUIT LOCATIONS REQUIRING ELECTROMIGRATION SHORT-LENGTH
A method is presented for forming a semiconductor structure. The method includes depositing an insulating layer over a semiconductor substrate, etching the...
2018/0114749 MULTI-LAYER LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel...
2018/0114748 SUBSTRATE INTERCONNECTIONS FOR PACKAGED SEMICONDUCTOR DEVICE
A "universal" substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the...
2018/0114747 Bonding of Laminates with Electrical Interconnects
A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each...
2018/0114746 INTEGRATED CIRCUIT PACKAGE SUBSTRATE
The present invention relates to an integrated circuit package substrate and, more specifically, to an integrated circuit package substrate, which exhibits...
2018/0114745 ELECTRONIC COMPONENT PACKAGE WITH HEATSINK AND MULTIPLE ELECTRONIC COMPONENTS
An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each...
2018/0114744 METHOD OF PRODUCING AN OPTOELECTRONIC COMPONENT AND OPTOELECTRONIC COMPONENT
A method of producing an optoelectronic component includes providing a lead frame having an upper side including a contact region and a chip reception region...
2018/0114743 STAGED VIA FORMATION FROM BOTH SIDES OF CHIP
A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of...
2018/0114742 HEAT SINK FASTENING SYSTEM AND METHOD
A system for mounting a heat sink to a printed circuit board includes a frame that is configured to be mounted to a printed circuit board and to receive a heat...
2018/0114741 ELECTRONIC DEVICE PACKAGE USING A SUBSTRATE SIDE COAXIAL INTERFACE
An electronic device is provided. In particular, the electronic device includes (i) an electronic integrated circuit (IC) chip, (ii) a chip mounting substrate...
2018/0114740 INVERTER
A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate...
2018/0114739 PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF
A manufacturing method including following steps is provided. A substrate that includes a core layer, a first conductive layer, and a second conductive layer...
2018/0114738 COOLING DEVICE AND MOUNTING METHOD
A cooling device comprises a frame and a heat radiating portion. The frame is mounted on a substrate, and includes a convex portion for cooling the substrate....
2018/0114737 TEMPERATURE CONTROL DEVICE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING THE...
A temperature control device for controlling a temperature of a semiconductor device including a first chip and a second chip. The temperature control device...
2018/0114736 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure includes a substrate, a chip, an encapsulant, a plurality of solder balls and a patterned metal layer. The substrate includes a first...
2018/0114735 SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS
A semiconductor apparatus 1 includes a circuit substrate 3 having a circuit pattern layer 3c on an upper principal surface, semiconductor elements 4a and 4b...
2018/0114734 CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The...
2018/0114733 METHOD AND APPARATUS FOR DETECTING AND REMOVING DEFECTIVE INTEGRATED CIRCUIT PACKAGES
A method for making integrated circuit (IC) packages includes providing a leadframe strip having a plurality of leadframe units and providing the leadframe...
2018/0114732 Process Modules Integrated Into a Metrology and/or Inspection Tool
Systems and methods for performing one or more processes on a specimen are provided. One system includes a deposition module incorporated into an existing tool...
2018/0114731 VERTICAL FIN FIELD EFFECT TRANSISTOR (V-FinFET), SEMICONDUCTOR DEVICE HAVING V-FinFET AND METHOD OF FABRICATING...
A vertical fin field effect transistor (V-FinFET) is provided as follows. A substrate has a lower source/drain (S/D). A fin structure extends vertically from...
2018/0114730 SPACER INTEGRATION SCHEME FOR NFET AND PFET DEVICES
The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of...
2018/0114729 FinFET EPI Channels Having Different Heights on a Stepped Substrate
A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure...
2018/0114728 COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND METHOD THEREOF
A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in...
2018/0114727 FIELD EFFECT TRANSISTOR WITH STACKED NANOWIRE-LIKE CHANNELS AND METHODS OF MANUFACTURING THE SAME
A CMOS circuit includes a partial GAA nFET and a partial GAA pFET. The nFET and the pFET each include a fin including a stack of nanowire-like channel regions...
2018/0114726 METHOD AND SYSTEM FOR VERTICAL INTEGRATION OF ELEMENTAL AND COMPOUND SEMICONDUCTORS
A method of fabricating a semiconductor structure includes providing an engineered substrate including a polycrystalline substrate, a barrier layer...
2018/0114725 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing semiconductor device comprises: applying a dual pulse power to the semiconductor device during metal electroplating a part of the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.