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Patent # Description
2018/0122733 METHOD FOR MANUFACTURING CIRCUIT REDISTRIBUTION STRUCTURE
A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias...
2018/0122732 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The...
2018/0122731 PLATED DITCH PRE-MOLD LEAD FRAME, SEMICONDUCTOR PACKAGE, AND METHOD OF MAKING SAME
An integrated circuit chip package and method for making the same, wherein the integrated circuit chip package includes conductive leads. The method includes...
2018/0122730 PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a...
2018/0122725 SEMICONDUCTOR DIE PACKAGE AND MANUFACTURING METHOD
In a general aspect, an apparatus can include a semiconductor die, a substrate, and a leadframe coupled to the substrate. The apparatus can include a...
2018/0122724 Semiconductor Device Having Leadframe With Pressure-Absorbing Pad Straps
A leadframe (300) for use in semiconductor devices, comprising an assembly pad (3010 having rectangular sides, the pad extending, on one pad side (301b), into...
2018/0122723 SEMICONDUCTOR DEVICE
A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the...
2018/0122722 SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME
A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring...
2018/0122721 PLUG STRUCTURE OF A SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME
A plug structure of a semiconductor chip includes a substrate, an insulating interlayer disposed on the substrate, wherein the insulating interlayer includes a...
2018/0122719 Apparatus for Manufacturing a Thermoelectric Module
An apparatus for manufacturing a thermoelectric module is provided. The thermoelectric module includes thermoelectric pellets, first electrodes, second...
2018/0122718 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the...
2018/0122717 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device, the method may include: forming a SOG film on a wafer, the wafer including a semiconductor substrate and a...
2018/0122716 ENVIRONMENTAL PROTECTION FOR WAFER LEVEL AND PACKAGE LEVEL APPLICATIONS
A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic...
2018/0122714 FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
2018/0122712 POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer...
2018/0122711 DUAL LINER SILICIDE
A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate...
2018/0122710 GATE HEIGHT AND SPACER UNIFORMITY
Embodiments are directed to a method of forming a semiconductor device and resulting structures having self-aligned spacer protection layers. The method...
2018/0122709 METHODS FOR FORMING A SEMICONDUCTOR DEVICE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
Methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an NMOS...
2018/0122708 FIN CUT DURING REPLACEMENT GATE FORMATION
A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a...
2018/0122706 FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN
A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a...
2018/0122703 STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS
A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second...
2018/0122700 WAFER PROCESSING METHOD
A wafer processing method divides a wafer into individual device chips along division lines. The method includes attaching an adhesive tape to the front side...
2018/0122699 MANUFACTURING METHOD OF ELECTRONIC COMPONENT
Provided is a manufacturing method of an electronic component, the manufacturing method including steps of: preparing a substrate having a first primary...
2018/0122698 THROUGH SUBSTRATE VIA (TSV) AND METHOD THEREFOR
A through substrate via (TSV) and method of forming the same are provided. The method of making the TSV may include etching a via opening into the backside of...
2018/0122697 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second...
2018/0122696 CO OR NI AND CU INTEGRATION FOR SMALL AND LARGE FEATURES IN INTEGRATED CIRCUITS
In one embodiment of the present disclosure, a microfeature workpiece includes at least two features of two different sizes disposed in a dielectric, wherein a...
2018/0122695 SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE
A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a...
2018/0122691 STRUCTURE AND METHOD TO IMPROVE FAV RIE PROCESS MARGIN AND ELECTROMIGRATION
A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel...
2018/0122690 IMAGE TONE-REVERSAL WITH A DIELECTRIC USING BOTTOM-UP CROSS-LINKING FOR BACK END OF LINE (BEOL) INTERCONNECTS
Image tone-reversal with a dielectric using bottom-up cross-linking for back end of line (BEOL) interconnects is described. In an example, a semiconductor...
2018/0122689 CONTACT MODULE FOR OPTIMIZING EMITTER AND CONTACT RESISTANCE
An advanced contact module for optimizing emitter and contact resistance and methods of manufacture are disclosed. The method includes forming a first contact...
2018/0122684 WAFER CHUCK FEATURING REDUCED FRICTION SUPPORT SURFACE
Grinding, lapping and polishing basically work by making scratches in the body being ground, lapped or polished. The scratches typically are linear. The...
2018/0122679 STRESS BALANCED ELECTROSTATIC SUBSTRATE CARRIER WITH CONTACTS
A substrate carrier with contacts is described that is balanced for thermal stress. In one example workpiece carrier has a rigid substrate configured to...
2018/0122677 HIGH DENSITY STOCKER
A substrate stocker system includes a high-density storage chamber that comprises one or more stacks of one or more substrates in a closed position, one or...
2018/0122676 Substrate Transfer Apparatus
A substrate transfer apparatus includes: a chamber including a lower surface, an upper surface opposing the lower surface, and a side surface extending between...
2018/0122672 TRANSFERRING APPARATUS AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT DEVICE
In one embodiment a transferring apparatus comprises a rail connected to a frame, a travelling part including a wheel that travels along the rail and a loading...
2018/0122670 REMOVABLE SUBSTRATE PLANE STRUCTURE RING
An apparatus may include a platen to hold a substrate. A substrate plane structure may be disposed in front of the platen. The substrate plane structure has an...
2018/0122669 OVERLAY MEASUREMENT METHOD AND APPARATUS
An apparatus for detecting a mark having first and second stripe groups on a substrate includes a detection module moveable over a surface of the substrate....
2018/0122668 APPARATUS AND METHOD FOR DETECTING OVERLAY MARK WITH BRIGHT AND DARK FIELDS
An apparatus for detecting a mark on a substrate is provided. The mark has a first stripe group and a second stripe group disposed in parallel to each other....
2018/0122667 CORE CONFIGURATION WITH ALTERNATING POSTS FOR IN-SITU ELECTROMAGNETIC INDUCTION MONITORING SYSTEM
An apparatus for chemical mechanical polishing includes a platen having a surface to support a polishing pad and an electromagnetic induction monitoring system...
2018/0122662 HEATING DEVICE
A heating device includes a base body 2 that has a placement surface 2a for placing a wafer W thereon; a heating resistor 4 that is embedded in the base body...
2018/0122661 HEATING DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS
A heating device is provided. The heating device includes a conveyance member that conveys a substrate between a heating position and a non-heating position, a...
2018/0122658 HEATING DEVICE
A heating device includes a base body that has a placement surface for placing a wafer thereon and a back surface that is on an opposite side of the placement...
2018/0122654 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower...
2018/0122647 Remote Hydrogen Plasma Titanium Deposition to Enhance Selectivity and Film Uniformity
Methods and apparatus to selectively deposit metal films (e.g., titanium films) are described. One of the precursors is energized to form ions and radicals of...
2018/0122646 LOW RESISTANCE SOURCE-DRAIN CONTACTS USING HIGH TEMPERATURE SILICIDES
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin disposed on a substrate. A...
2018/0122644 HARD MASK LAYER TO REDUCE LOSS OF ISOLATION MATERIAL DURING DUMMY GATE REMOVAL
A method includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with active region(s)...
2018/0122640 SCREEN-PRINTABLE BORON DOPING PASTE WITH SIMULTANEOUS INHIBITION OF PHOSPHORUS DIFFUSION IN CO-DIFFUSION PROCESSES
The present invention relates to a novel printable boron doping paste in the form of a hybrid gel based on precursors of inorganic oxides, preferably of...
2018/0122639 METHOD FOR MANUFACTURING BONDED SOI WAFER
A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer,...
2018/0122638 SUBSTRATE PROCESSING APPARATUS
Disclosed is a substrate processing apparatus comprising: a chamber which provides a substrate processing space; a process gas supply line which is for...
2018/0122636 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
The present disclosure is directed to a manufacturing method of a semiconductor device. The manufacturing method includes: providing an initial structure...
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