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Patent # Description
2018/0130840 SOLID-STATE IMAGE PICKUP APPARATUS AND IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP APPARATUS
A solid-state image pickup apparatus includes a photoelectric conversion unit, a charge storage unit, and a floating diffusion unit, all disposed on a...
2018/0130839 METHODS AND APPARATUS FOR AN IMAGE SENSOR WITH A MULTI-BRANCH TRANSISTOR
Various embodiments of the present technology may comprise a method and device for a multi-branch transistor for use in an image sensor. The device may...
2018/0130838 Layout and operation of pixels for image sensors
Various embodiments include methods and apparatuses for forming and using pixels for image sensors. In one embodiment, an image sensor having at least two...
2018/0130837 IMAGE SENSOR
An image sensor may include a pixel array. The pixel array may include a plurality of sub pixel arrays arranged two-dimensionally, wherein each of the...
2018/0130836 INTERCONNECT STRUCTURE FOR STACKED DEVICE AND METHOD
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor...
2018/0130835 IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING IMAGE PICKUP ELEMENT, AND ELECTRONIC APPARATUS
An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in...
2018/0130834 IMAGE SENSOR AND METHODS FOR FABRICATING THE SAME
Disclosed is an image sensor, which includes a first PD isolation region for determining first to fourth PD regions, an FD isolation region formed between the...
2018/0130833 SOLID-STATE IMAGE PICKUP UNIT, METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP UNIT, AND ELECTRONIC APPARATUS
A solid-state image pickup unit includes: a p-type compound semiconductor layer of a chalcopyrite structure; an electrode formed on the p-type compound...
2018/0130832 LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
An LTPS array substrate includes: a substrate on which a gate is disposed. An insulating layer and a polycrystalline silicon layer are disposed in sequence on...
2018/0130831 LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first...
2018/0130830 LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME
An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array...
2018/0130829 PRINTABLE DEVICE WAFERS WITH SACRIFICIAL LAYERS
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the...
2018/0130828 DISPLAY DEVICE
A display device having a gate driver which may reduce generation of ripple at the output of the gate drive includes: a substrate; and a driver circuit...
2018/0130827 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE HAVING THE SAME
A thin film transistor includes a first blocking layer disposed on a substrate, and an active pattern disposed on the first blocking layer. The active pattern...
2018/0130826 METHOD OF MANUFACTURING TOP-GATE THIN FILM TRANSISTOR AND TOP-GATE THIN FILM TRANSISTOR THEREOF
A method of manufacturing a top-gate thin film transistor and a top-gate thin film transistor thereof are described. The method of manufacturing a top-gate...
2018/0130825 PIXEL ARRAY
A pixel array includes first signal lines, second signal lines, active elements, pixel electrodes, and selection lines. The second signal lines are intersected...
2018/0130824 DISPLAY PANEL, PIXEL ARRAY SUBSTRATE AND LINE ARRAY STRUCTURE
A line array structure is provided, including long wirings, short wirings, first dummy wirings and connection lines. The substrate has an elongated region, a...
2018/0130823 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Disclosed is a method of manufacturing a nonvolatile memory device. In the method, a stacked structure is formed on a conductive substrate structure. The...
2018/0130822 PROCESS FOR FABRICATING 3D MEMORY
A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A...
2018/0130821 VERTICAL MEMORY DEVICE
A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements...
2018/0130820 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a first electrode layer extending in a first direction, a second electrode layer above the first electrode layer and...
2018/0130819 MEMORY DEVICES AND SYSTEMS HAVING REDUCED BIT LINE TO DRAIN SELECT GATE SHORTING AND ASSOCIATED METHODS
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
2018/0130818 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a cell array region formed on a substrate, a word line contact region, and a page buffer region coupled to the cell...
2018/0130817 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided herein is a method of manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: alternately stacked first...
2018/0130816 SEMICONDUCTOR DEVICE INCLUDING CHANNEL STRUCTURE
A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate...
2018/0130815 TRANSISTORS HAVING DIELECTRIC MATERIAL CONTAINING NON-HYDROGENOUS IONS AND METHODS OF THEIR FABRICATION
Methods for fabricating a transistor include forming a dielectric material adjacent to a semiconductor, introducing non-hydrogenous ions into the dielectric...
2018/0130814 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes gate stacked structures surrounding channel layers, a common source line filling a separation area between the gate stacked...
2018/0130813 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged...
2018/0130812 THREE-DIMENSIONAL MEMORY DEVICE WITH ELECTRICALLY ISOLATED SUPPORT PILLAR STRUCTURES AND METHOD OF MAKING THEREOF
A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First...
2018/0130811 SIMPLE INTEGRATION OF NON-VOLATILE MEMORY AND COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
A method that allows integrating complementary metal oxide semiconductor (CMOS) transistors and a non-volatile memory (NVM) transistor on a single substrate is...
2018/0130810 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an ...
2018/0130809 METHOD OF WRITING TO MEMORY CIRCUIT USING RESISTIVE DEVICE
A method, of writing to a memory cell, includes: causing a pulling device of the memory cell to pull a voltage level at a first data node of the memory cell...
2018/0130808 INTEGRATED CIRCUIT DEVICES INCLUDING FIN SHAPES
Integrated circuit devices are provided. An integrated circuit device includes a substrate having first and second fin-shaped Field Effect Transistor (FinFET)...
2018/0130807 Transistors and Memory Arrays
Some embodiments include a transistor having a semiconductor material with a trench extending downwardly therein. The semiconductor material has a first post...
2018/0130806 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including an active region and an element isolation region defining the active region, a gate trench extending into...
2018/0130805 SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE AND METHOD OF FABRICATING THE SAME
A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the...
2018/0130804 Vertical Thyristor Cell and Memory Array with Silicon Germanium Base Regions
Memory arrays of vertical thyristor memory cells with SiGe base layers are described. The composition of the SiGe can be constant or varied depending upon the...
2018/0130803 METHOD AND CIRCUIT FOR INTEGRATED CIRCUIT BODY BIASING
The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices...
2018/0130802 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure...
2018/0130801 WELL-BASED INTEGRATION OF HETEROEPITAXIAL N-TYPE TRANSISTORS WITH P-TYPE TRANSISTORS
Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin...
2018/0130800 Forming Doped Regions in Semiconductor Strips
A method includes etching a semiconductor substrate to form trenches, with a portion of the semiconductor substrate between the trenches being a semiconductor...
2018/0130799 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A STANDARD CELL WHICH INCLUDES A FIN
Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line...
2018/0130798 MOSFET TRANSISTORS WITH ROBUST SUBTHRESHOLD OPERATIONS
An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region...
2018/0130797 MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE
One embodiment of the instant disclosure provides a semiconductor structure that comprises: a first device layer including a first active layer disposed over a...
2018/0130796 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a first region and a second region, a cell gate pattern on the first region of the substrate, a dummy...
2018/0130795 ULTRASONIC TRANSDUCERS IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) WAFERS AND RELATED APPARATUS AND METHODS
Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices....
2018/0130794 ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT AND MOTOR ASSEMBLY
An electronic circuit includes an output port, a first AC input port and a second AC input port connecting with an external AC power source, a rectifier...
2018/0130793 Electrostatic Discharge Device and Split Multi Rail Network with Symmetrical Layout Design Technique
A symmetrical layout technique for an electrostatic discharge ESD device and a corresponding power supply network is presented. The ESD device protects an...
2018/0130792 SYSTEM AND METHOD OF FABRICATING ESD FINFET WITH IMPROVED METAL LANDING IN THE DRAIN
A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the...
2018/0130791 ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT AND MOTOR ASSEMBLY
An electronic circuit includes an output port, a first AC input port and a second AC input port connecting with an external AC power source, a rectifier...
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