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Patent # Description
2018/0129626 DYNAMIC CLOCK LANE ASSIGNMENT FOR INCREASED PERFORMANCE AND SECURITY
A lane within a processor bus that communicatively connects a transmitter and a receiver is dynamically assigned as a clock lane. The clock lane subsequently...
2018/0129625 WIRELESS GIGABIT ALLIANCE (WIGIG) ACCESSORIES
Example implementations relate to wireless gigabit alliance (WiGig) enabled computing systems including WiGig accessories. In one example, a WiGig accessory...
2018/0129624 METHOD AND APPARATUS FOR HANDLING OUTSTANDING INTERCONNECT TRANSACTIONS
A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction...
2018/0129623 LINK ROLE DETERMINATION IN A DUAL-MODE PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) DEVICE
Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a...
2018/0129622 SYSTEMS AND METHODS FOR ENABLING COMMUNICATION BETWEEN AN ACCESSORY CHARGER ADAPTER (ACA) AND AN ACA-AGNOSTIC...
A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus...
2018/0129621 APPARATUS AND METHOD FOR ACCESSING DATA IN MEMORY
Disclosed are a direct memory access (DMA) apparatus and method. The DMA apparatus may include memory, a buffer, a DMA controller suitable for setting group...
2018/0129620 PROGRAMMABLE MEMORY TRANSFER REQUEST PROCESSING UNITS
An apparatus (100) comprising a programmable memory transfer request processing (PMTRP) unit (120) and a programmable direct memory access (PDMA) unit (140)....
2018/0129619 VIRTUALIZING INTERRUPT PRIORITIZATION AND DELIVERY
Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes...
2018/0129618 METHOD AND DEVICES FOR CONTROLLING OPERATIONS OF A CENTRAL PROCESSING UNIT
Control circuitry controls the operations of a central processing unit, CPU, which is associated with a nominal clock frequency. The CPU is further coupled to...
2018/0129617 MEMORY CARD READING METHOD WHICH ADJUSTS READER TO HOST INTERFACE
A memory card reading method applied to an electronic device, includes: detecting a specification information of a memory card, wherein the specification...
2018/0129616 SYSTEMS AND METHODS FOR ISOLATING INPUT/OUTPUT COMPUTING RESOURCES
Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include logic to identify a...
2018/0129615 METHOD AND APPARATUS FOR SWITCHING INPUT CHARACTER IN WFD
A method and an apparatus for switching an input character in a WFD are disclosed. The method for switching an input character in a WFD comprises the steps of:...
2018/0129614 INFORMATION PROCESSING APPARATUS CAPABLE OF BACKING UP AND RESTORING KEY FOR DATA ENCRYPTION AND METHOD FOR...
An information processing apparatus includes a storage device configured to store data, an encryption chip configured to store an encryption key therein, a...
2018/0129613 CACHE MEMORY ARCHITECTURE AND POLICIES FOR ACCELERATING GRAPH ALGORITHMS
A cache memory may be configured to store a plurality of lines, where each line includes data and metadata. A circuit may be configured to determine a...
2018/0129612 DETECTION OF AVOIDABLE CACHE THRASHING FOR OLTP AND DW WORKLOADS
Techniques are provided to adjust the behavior of a cache based on a count of cache misses for items recently evicted. In an embodiment, a computer responds to...
2018/0129611 DATA PROCESSING APPARATUS AND METHOD WITH OWNERSHIP TABLE
A data processing apparatus (20) comprises processing circuitry (24, 25, 28) to execute a plurality of processes. An ownership table (50) comprises one or more...
2018/0129610 METHOD TO SHARE A COHERENT ACCELERATOR CONTEXT INSIDE THE KERNEL
Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first...
2018/0129609 METHOD TO SHARE A COHERENT ACCELERATOR CONTEXT INSIDE THE KERNEL
Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. A request is received from a first...
2018/0129608 Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the...
2018/0129607 VARIABLE CACHING STRUCTURE FOR MANAGING PHYSICAL STORAGE
A method for managing a variable caching structure for managing storage for a processor. The method includes using a multi-way tag array to store a plurality...
2018/0129606 MEMORY ACCESS ARCHITECTURE WITH COHERENCE
Disclosed aspects relate to a computer system having a plurality of processor chips and a plurality of memory buffer chips, and for transferring data in the...
2018/0129605 INFORMATION PROCESSING DEVICE AND DATA STRUCTURE
An information processing device of an embodiment has an input unit, a storage unit, a read control unit, and a write control unit. A read request and a write...
2018/0129604 STORAGE DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME
A data storage device and a method for operating the data storage device are disclosed. The data storage device may include an interface receiving a command...
2018/0129603 ELECTRONIC DEVICE AND METHOD FOR ACCESSING MEMORY
An electronic device including a volatile memory configured to include a plurality of memory rows, the volatile memory including a data bit of a predetermined...
2018/0129602 GARBAGE COLLECTION METHOD FOR DATA STORAGE DEVICE
A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source...
2018/0129601 VOLTAGE CONTROL CIRCUIT FOR PROVIDING TWO VOLTAGES GENERATED BASED ON A PARAMETER CORRESPONDING TO AN INPUT SIGNAL
Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the...
2018/0129600 MEMORY SYSTEM AND CONTROL METHOD
A memory system includes a nonvolatile memory having memory dies controlled in parallel and each including a plurality of physical blocks, and a controller....
2018/0129599 MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL)...
2018/0129598 ELECTRONIC DEVICE AND MEMORY ALLOCATION METHOD THEREFOR
An electronic device according to an embodiment of the present disclosure comprises: a memory including a plurality of pages; and a controller selecting a page...
2018/0129597 IDENTIFYING INCORRECT VARIABLE VALUES IN SOFTWARE TESTING AND DEVELOPMENT ENVIRONMENTS
A test suite is executed to test a computer program for a plurality of variables. A variable value is generated for each variable of the plurality of variables...
2018/0129596 IDENTIFYING INCORRECT VARIABLE VALUES IN SOFTWARE TESTING AND DEVELOPMENT ENVIRONMENTS
A test suite is executed to test a computer program for a plurality of variables. A variable value is generated for each variable of the plurality of variables...
2018/0129595 METHOD OF AUTOMATICALLY TESTING SMART DEVICE APPLICATION PROGRAM USING PERMISSION BOOSTER
The present invention relates to a method of testing an application program mounted on a smart device 10 such as a smart phone, a tablet computer or the like,...
2018/0129594 System and Method for Test Case Generation and Adaptation
A system and method for generating and adapting a test case is provided. The system may process an application prototype to extract information regarding the...
2018/0129593 CROSS-PLATFORM API TEST FLOW SYNTHESIZER
A system, method, and computer-readable medium, including obtaining a plurality of different application program interfaces (APIs), one for each of a plurality...
2018/0129592 MOCK-BASED UNIT TEST(S) FOR AN END-TO-END TEST OF A CODE SNIPPET
Techniques are described herein that are capable of generating mock-based unit test(s) for an end-to-end test of a code snippet (a.k.a. system to test (STT))....
2018/0129591 CODE COVERAGE THROUGH OVERLAY HOOKS
In an approach for utilizing overlay hooks to increase code coverage, a processor inserts an overlay hook in program code at a location within the program code...
2018/0129590 SYSTEM AND METHOD FOR DETERMINING TEST COVERAGE
A computer-implemented method, computer program product, and system is provided for determining test coverage. In an implementation, a method may include...
2018/0129589 Systems and Methods for Summarization and Visualization of Trace Data
Systems and methods for visualizing and/or analyzing trace data collected during execution of a computer system are described. Algorithms and user interface...
2018/0129588 Creation and Utilization of Ephemeral Organization Structures in a Multitenant Environment
Techniques and architectures for scratch organizations in a multitenant environment. A first scratch organization is generated based on a designated set of...
2018/0129587 Declarative Signup for Ephemeral Organization Structures in a Multitenant Environment
Techniques and architectures for creating scratch organizations in a multitenant environment. A scratch organization defined by metadata corresponding to a...
2018/0129586 METHOD OF, AND APPARATUS FOR, HANDLING REFERENCE IMAGES FOR AN AUTOMATED TEST OF SOFTWARE WITH A GRAPHICAL USER...
A method for performing an automated computer test that causes a test computer system to control a graphical user interface (GUI) of a system under test (SUT)....
2018/0129585 FORMATION AND MANIPULATION OF TEST DATA IN A DATABASE SYSTEM
Systems and methods are provided for creating a sandbox for an original tenant at a point in time, the original tenant having original tenant data stored in an...
2018/0129583 FUNCTION CALL VISUALIZATION
In one example in accordance with the present disclosure, a system may include a processor and a memory comprising instructions executable by the processor to...
2018/0129582 DEBUGGING A LIVE STREAMING APPLICATION
A connection can be made to a processing element of a remotely deployed and live streaming application executed by a first data processing system, the...
2018/0129581 METHOD FOR STATIC AND DYNAMIC CONFIGURATION VERIFICATION
According to an aspect of some embodiments of the present invention there is provided a method for verifying correctness of application configuration of an...
2018/0129580 DEBUGGING IN A PRIVATE CLOUD ENVIRONMENT
The present disclosure involves systems, software, and computer implemented methods for remotely debugging applications in a private cloud environment. One...
2018/0129579 Systems and Methods with a Realtime Log Analysis Framework
Systems and methods are disclosed for processing a stream of logged data by: creating one or more models from a set of training logs during a training phase;...
2018/0129578 VERIFYING A GRAPH-BASED COHERENCY VERIFICATION TOOL
Verification is provided of a functional correctness of a graph-based coherency verification tool for logic designs of arrangements of processors and processor...
2018/0129577 TESTING SPECULATIVE INSTRUCTION EXECUTION WITH TEST CASES PLACED IN MEMORY SEGMENTS WITH NON-NATURALLY ALIGNED...
Test cases for testing speculative execution of instructions are replicated into a memory with non-naturally aligned data boundaries to create a non-contiguous...
2018/0129576 HANDLING DEGRADED CONDITIONS USING A REDIRECT MODULE
A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN), the method begins by receiving...
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