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Patent # Description
2018/0145090 TFT SUBSTRATE AND TOUCH DISPLAY PANEL USING SAME
A TFT substrate for a touch display panel of reduced thickness defines a display area and a surrounding non-display area. The TFT substrate includes a first...
2018/0145089 REFLECTIVE LIQUID CRYSTAL DISPLAY PANEL
A reflective LCD panel includes a plurality of pixel units, each of which includes: first and second substrates, first and second scan lines, first and second...
2018/0145088 FIELD-EFFECT TRANSISTORS WITH A BURIED BODY CONTACT
Device structures for a field-effect transistor with a body contact and methods of forming such device structures. An opening is formed that extends through a...
2018/0145087 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure,...
2018/0145086 DRY ETCHING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first...
2018/0145085 LOGIC-COMPATIBLE MEMORY CELL MANUFACTURING METHOD AND STRUCTURE THEREOF
The present disclosure presents a method of manufacturing a semiconductor structure, in which a memory cell is formed on a semiconductor substrate, the memory...
2018/0145084 Memory Cells
A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor...
2018/0145083 CONTROLLED MODIFICATION OF ANTIFUSE PROGRAMMING VOLTAGE
The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate...
2018/0145082 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode...
2018/0145081 STATIC RANDOM ACCESS MEMORY UNIT CELL
The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second...
2018/0145080 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device including a substrate; a trench formed within the substrate; a gate insulating film formed conformally along a portion of a surface of...
2018/0145079 METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH ENGINEERED DOPANT PROFILES
Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at...
2018/0145078 INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
An integrated circuit device includes a substrate, first and second fin-type active areas which extend in a first direction on the substrate, first and second...
2018/0145077 HIGH-MOBILITY SEMICONDUCTOR SOURCE/DRAIN SPACER
Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a...
2018/0145076 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE
A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure...
2018/0145075 Methods, Structures, and Designs for Self-Aligning Local Interconnects Used in Integrated Circuits
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of...
2018/0145074 Multi-Gate FETs and Methods for Forming the Same
A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top...
2018/0145073 METAL LAYER ROUTING LEVEL FOR VERTICAL FET SRAM AND LOGIC CELL SCALING
Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of...
2018/0145071 DECOUPLING CAPACITOR WITH METAL PROGRAMMABLE KNEE FREQUENCY
A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is...
2018/0145070 Electromigration Resistant Semiconductor Device
A semiconductor device includes first and second transistors, a pair of first source/drain regions, a pair of second source/drain regions, and a cell. Each of...
2018/0145069 SEMICONDUCTOR RESISTOR AND MANUFACTURING METHOD THEREFOR
The present disclosure relates to a technical field of semiconductors and discloses a semiconductor resistor and a manufacturing method therefor. The method...
2018/0145068 AC-COUPLED SWITCH AND METAL CAPACITOR STRUCTURE FOR NANOMETER OR LOW METAL LAYER COUNT PROCESSES
Alternating Current (AC)-coupled switch and metal capacitor structures for nanometer or low metal layer count processes are provided. According to one aspect...
2018/0145067 METHOD OF FORMING BANDGAP REFERENCE INTEGRATED CIRCUIT
A method of forming an integrated circuit comprises forming a first doped region and a second doped region in a substrate. The second doped region is formed...
2018/0145066 ESD PROTECTION CIRCUIT
An electrostatic discharge (ESD) protection circuit includes a silicon controlled rectifier (SCR) configured to discharge an ESD current applied to a power...
2018/0145065 CARRRIER BYPASS FOR ELECTROSTATIC DISCHARGE
Various aspects of the disclosure are directed to circuitry that may be used to shunt current. As may be consistent with one or more embodiments a first...
2018/0145064 SELF-BIASED BIDIRECTIONAL ESD PROTECTION CIRCUIT
Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected...
2018/0145063 INTEGRATED CIRCUIT LAYOUT USING LIBRARY CELLS WITH ALTERNATING CONDUCTIVE LINES
An integrated circuit layout is described that uses a library cells with alternating conducting lines. One embodiment includes a first cell and a second cell,...
2018/0145062 PASSIVE-ON-GLASS (POG) DEVICE AND METHOD
A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via...
2018/0145061 SEMICONDUCTOR PACKAGE
A semiconductor package includes a semiconductor chip disposed on a first substrate, a mold layer covering a sidewall of the semiconductor chip and including a...
2018/0145060 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS
A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive...
2018/0145059 LIGHT EMITTING DIODE (LED) DEVICES, COMPONENTS AND METHODS
Devices, components and methods containing one or more light emitter devices, such as light emitting diodes (LEDs) or LED chips, are disclosed. In one aspect,...
2018/0145058 Method for Producing a Semiconductor Component and a Semiconductor Component
A method for producing a plurality of semiconductor components and a semiconductor component are disclosed. In an embodiment the component includes a light...
2018/0145057 Fabrication Method for Emissive Display with Light Management System
A method is provided for fabricating an emissive display substrate with a light management system. The method provides a transparent first substrate with a top...
2018/0145056 LED MODULE AND METHOD FOR FABRICATING THE SAME
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding...
2018/0145055 METHOD FOR INTERCONNECTING STACKED SEMICONDUCTOR DEVICES
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
2018/0145054 SEMICONDUCTOR PACKAGE
A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first...
2018/0145053 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes a package substrate, semiconductor chips stacked on the package substrate, and electrical connectors that connect internal...
2018/0145052 GAN DEVICES ON ENGINEERED SILICON SUBSTRATES
GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon...
2018/0145051 PACKAGE-BOTTOM THROUGH-MOLD VIA INTERPOSERS FOR LAND-SIDE CONFIGURED DEVICES FOR SYSTEM-IN-PACKAGE APPARATUS
A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package...
2018/0145050 Three-Dimensional Package Structure and the Method to Fabricate Thereof
A three-dimensional package structure, comprising: a substrate; a first plurality of discrete electronic components disposed over the bottom surface of the...
2018/0145049 STACKED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package...
2018/0145048 METHOD FOR APPLYING A BONDING LAYER
A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of...
2018/0145047 HIGH DENSITY SUBSTRATE ROUTING IN PACKAGE
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
2018/0145046 Interconnect Structure and Method of Forming Same
A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first...
2018/0145045 Terminal Structure of a Power Semiconductor Device
A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor...
2018/0145044 ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME
An electronic component package and a method of manufacturing the same are provided. The electronic component package includes a frame having a through-hole,...
2018/0145043 RF Power Package Having Planar Tuning Lines
An RF power package includes a substrate having a metallized part and an insulating part, an RF power transistor die embedded in or attached to the substrate,...
2018/0145042 INDUCTOR INTERCONNECT
A device and method of utilizing spiral interconnects for voltage and power regulation are shown. Examples of spiral interconnects include air core inductors....
2018/0145041 SELF-TEST CAPABLE INTEGRATED CIRCUIT APPARATUS AND METHOD OF SELF-TESTING AN INTEGRATED CIRCUIT
A self-test capable integrated circuit apparatus includes a pattern generator, a results store and testable logic. The testable logic includes a plurality of...
2018/0145040 METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED...
An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor...
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