Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
2018/0145039 METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT,...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The...
2018/0145038 METHODS FOR FORMING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
A method for forming a semiconductor device and semiconductor device is disclosed. In one example, the method includes forming a silicone layer on a...
2018/0145037 SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate...
2018/0145036 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole of the first...
2018/0145035 DORIC PILLAR SUPPORTED MASKLESS AIRGAP STRUCTURE FOR CAPACITANCE BENEFIT WITH UNLANDED VIA SOLUTION
Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a...
2018/0145034 Methods To Selectively Deposit Corrosion-Free Metal Contacts
Methods of forming a contact line comprising cleaning the surface of a cobalt film in a trench and forming a protective layer on the surface of the cobalt, the...
2018/0145033 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, at least one...
2018/0145032 INTEGRATED FAN-OUT PACKAGING
The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer,...
2018/0145031 MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME
A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first...
2018/0145030 INTEGRATED CIRCUIT CHIP WITH POWER DELIVERY NETWORK ON THE BACKSIDE OF THE CHIP
An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground...
2018/0145029 METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING STAIRCASE STRUCTURES
A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at...
2018/0145028 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate, a first metal layer, an insulation layer, an organic layer, and a second metal layer. The first...
2018/0145027 METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT...
An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The...
2018/0145026 METHOD FOR ADJUSTING CIRCUIT CHARACTERISTICS WITH TRIMMING TECHNOLOGY IN INTEGRATED CIRCUITS
An integrated circuit includes: a fuse; a reference resistance generator configured to receive a mode signal indicating whether the integrated circuit is...
2018/0145025 Stress Reduction Apparatus
A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second...
2018/0145024 INTEGRATED SHIELDING AND DECOUPLING CAPACITOR STRUCTURE
A shielding and decoupling capacitor structure can be fabricated within an integrated circuit (IC) by forming recesses in a top surface of a dielectric layer...
2018/0145023 SEMICONDUCTOR DEVICE AND AMPLIFIER APPARATUS
A semiconductor device that outputs a radio-frequency (RF) signal with high power is disclosed. The semiconductor device includes a housing, a semiconductor...
2018/0145022 Through Via Structure and Method
A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a...
2018/0145021 THROUGH VIA STRUCTURE AND MANUFACTURING METHOD THEREOF
A through via structure includes a conductive wiring, at least one dielectric layer over the conductive wiring, a via hole in the at least one dielectric layer...
2018/0145020 SEMICONDUCTOR DEVICE
This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor...
2018/0145019 METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING THE SAME
Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the...
2018/0145018 SEMICONDUCTOR DEVICES AND PACKAGE STRUCTURES COMPRISING THE SAME
A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer;...
2018/0145017 SEMICONDUCTOR SUBSTRATE INCLUDING EMBEDDED COMPONENT AND METHOD OF MANUFACTURING THE SAME
A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of...
2018/0145016 MULTIPLE-COMPONENT SUBSTRATE FOR A MICROELECTRONIC DEVICE
Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is...
2018/0145015 METHOD OF FABRICATING PACKAGING LAYER OF FAN-OUT CHIP PACKAGE
A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the...
2018/0145014 HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAYER (BBUL) PACKAGING TECHNOLOGY
An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive...
2018/0145013 METHODS OF FORMING LEADLESS SEMICONDUCTOR PACKAGES WITH PLATED LEADFRAMES AND WETTABLE FLANKS
A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate...
2018/0145012 Robust Through-Silicon-Via Structure
Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect...
2018/0145011 FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)
Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is...
2018/0145010 Electronic Assemblies Having A Cooling Chip Layer With Impingement Channels And Through Substrate Vias
An electronics assembly includes a cooling chip structure having a target layer and a jet impingement layer coupled to the target layer. The jet impingement...
2018/0145009 Electronic Assemblies Having A Cooling Chip Layer With Fluid Channels And Through Substrate Vias
An electronics assembly includes a cooling chip structure having a device facing surface opposite a base surface and one or more sidewalls extending around a...
2018/0145008 DIELECTRIC HEAT PATH DEVICES, AND SYSTEMS AND METHODS USING THE SAME
Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a...
2018/0145007 POWER MODULE AND FABRICATION METHOD OF THE SAME, GRAPHITE PLATE, AND POWER SUPPLY EQUIPMENT
A power module (PM) includes: an insulating substrate; a semiconductor device disposed on the insulating substrate, the semiconductor device including...
2018/0145006 THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME
Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal...
2018/0145005 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING METHOD
A semiconductor device of the present invention includes: a substrate (12) that is annular or partially annular, the substrate (12) having an inner...
2018/0145004 WIRING BOARD, AND MANUFACTURING METHOD
The present disclosure relates to a wiring board and a manufacturing method that simultaneously solve problems of stress and heat release A wiring board as one...
2018/0145003 ELECTRONIC COMPONENT MOUNTING PACKAGE AND ELECTRONIC DEVICE USING THE SAME
An electronic component mounting package includes a dielectric substrate between first portions of a pair of signal terminals that protrude from one side in a...
2018/0145002 DIE EDGE INTEGRITY MONITORING SYSTEM
An edge crack monitoring system for an integrated circuit provided on a die, comprises a conductive trace comprising at least a first conductive path for...
2018/0145001 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening...
2018/0145000 ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS
An ion implantation method includes measuring a beam energy of an ion beam that is generated by a high-energy multistage linear acceleration unit operating in...
2018/0144999 METHOD OF SEMICONDUCTOR WAFER BONDING AND SYSTEM THEREOF
A method of semiconductor wafer bonding and system thereof are proposed. A first alignment mark of a first semiconductor wafer is aligned with a second...
2018/0144998 INSPECTION APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
Disclosed are an inspection apparatus and a method of manufacturing a semiconductor device using the same. The inspection apparatus includes a stage configured...
2018/0144997 SAMPLE WITH IMPROVED EFFECT OF BACKSIDE POSITIONING, FABRICATION METHOD AND ANALYSIS METHOD THEREOF
A sample with improved effect of backside positioning, fabrication method and analysis method thereof are disclosed in the present invention. The present...
2018/0144996 SYSTEM, METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR TUNING SENSITIVIES OF, AND DETERMINNG A PROCESS...
A system, method, and non-transitory computer readable medium are provided for tuning sensitivities of, and determining a process window for, a modulated...
2018/0144995 OPTICAL INSPECTION APPARATUS AND METHOD AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE APPARATUS
An optical inspection apparatus includes a broadband light source, a monochromator, an image obtaining apparatus, and an analysis device. The monochromator is...
2018/0144994 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A method of manufacturing a semiconductor device is provided as follows. A fin and an isolation surrounding a lower portion of the fin are formed on a...
2018/0144993 DEVICES AND METHODS RELATED TO RADIO-FREQUENCY SWITCHES HAVING IMPROVED ON-RESISTANCE PERFORMANCE
Devices and methods related to radio-frequency (RF) switches having improved on-resistance performance. In some embodiments, a switching device can include a...
2018/0144992 METHOD OF FABRICATION OF A FET TRANSISTOR HAVING AN OVERLAPPED GATE
A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate...
2018/0144991 CO-INTEGRATION OF TENSILE SILICON AND COMPRESSIVE SILICON GERMANIUM
Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include ...
2018/0144990 METHOD OF FINFET CONTACT FORMATION
A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.