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Patent # Description
2018/0151713 HEMT HAVING CONDUCTION BARRIER BETWEEN DRAIN FINGERTIP AND SOURCE
A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region...
2018/0151712 ENHANCEMENT MODE HEMT DEVICE
Provided is an enhancement mode HEMT device including a substrate, a channel layer, a barrier layer, a nitride field plate, a P-type semiconductor layer, a...
2018/0151711 SEMICONDUCTOR DEVICE, RC-IGBT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device 100 includes a semiconductor substrate 1 including a first principal surface and a second principal...
2018/0151710 TRENCH GATE IGBT
Disclosed is a trench gate IGBT. A dummy gate is arranged between two real gates. An emitter metal is in contact with the dummy gate, so that an emitter metal...
2018/0151709 SEMICONDUCTOR DEVICE, SUBSTRATE AND ELECTRICAL POWER CONVERSION DEVICE
An n-type drift layer DRL formed on a buffer layer BUF in a semiconductor device (SiC-IGBT) is configured so as to have (c1) an n-type first drift region DRL1...
2018/0151708 SWITCHING CIRCUIT
A switching circuit may be provided with: a parallel circuit including a first IGBT and a second IGBT connected in parallel; a controller configured to receive...
2018/0151707 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate...
2018/0151706 FINFET DEVICE AND METHODS OF FORMING
A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending...
2018/0151705 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a...
2018/0151704 FinFET Devices and Methods of Forming
A finFET device and methods of forming a finFET device are provided. The method includes forming a capping layer over a fin of a fin field effect transistor...
2018/0151703 FETS AND METHODS OF FORMING FETS
An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region...
2018/0151702 MULTI-HEIGHT FINFET DEVICE BY SELECTIVE OXIDATION
A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base...
2018/0151701 FINFET Device and Methods of Forming
A finFET device and methods of forming a finFET device are provided. The method includes forming a first gate spacer is formed over a dummy gate of a fin field...
2018/0151700 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first...
2018/0151699 Semiconductor Device and Method of Manufacture
A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the...
2018/0151698 EPITAXIAL FIN STRUCTUES OF FINFET
A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin...
2018/0151697 Sidewall Spacers for Self-Aligned Contacts
A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a...
2018/0151696 SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
A semiconductor device and its manufacturing method are presented. The manufacturing method includes providing a semiconductor structure comprising a...
2018/0151695 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A FinFET device structure and method for forming the same are provided. The method includes forming a fin structure over a substrate and forming a dummy gate...
2018/0151694 Semiconductor Device and Methods of Manufacture
A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process....
2018/0151693 FinFET Device and Method of Forming the Same
A method may include depositing a first conductive material in an opening disposed between a first semiconductor structure and a second semiconductor...
2018/0151692 High Electron Mobility Transistor and Method of Forming the Same
A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different...
2018/0151691 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, at least one gate, and an insulating structure. The substrate includes at least one semiconductor fin. The gate is...
2018/0151690 MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS
Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor....
2018/0151689 SPACERS FOR TIGHT GATE PITCHES IN FIELD EFFECT TRANSISTORS
Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a...
2018/0151688 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a...
2018/0151687 APPARATUS AND METHOD OF FABRICATING LIGHTING APPARATUS USING ORGANIC LIGHT EMITTING DEVICE
A film having a plurality of lighting devices thereon is transferred between a film supplying roll and a film collecting roll, and an organic light emitting...
2018/0151686 FINFET WITH REDUCED PARASITIC CAPACITANCE
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed...
2018/0151685 METHOD OF FORMING SEMICONDUCTOR DEVICE
A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then...
2018/0151684 METHOD TO FORM OHMIC CONTACTS TO SEMICONDUCTORS USING QUANTIZED METALS
An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least...
2018/0151683 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second...
2018/0151682 Semiconductor Device and Method
A vertical gate all around (VGAA) is provided. In embodiments, the VGAA has a nanowire with a first contact pad and a second contact pad. A gate electrode is...
2018/0151681 Normally Off HEMT with Self Aligned Gate Structure
A heterostructure body with a buffer region, and a barrier region disposed on the buffer region is provided. A gate trench is formed in the barrier region. A...
2018/0151680 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate...
2018/0151679 LOW RESISTANT CONTACT METHOD AND STRUCTURE
A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine,...
2018/0151678 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a source/drain feature, a gate structure, a contact, a gate spacer, and a contact spacer. The source/drain feature...
2018/0151677 SUB-FIN SIDEWALL PASSIVATION IN REPLACEMENT CHANNEL FINFETS
Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques...
2018/0151676 Method for Manufacturing a Semiconductor Device
A method for manufacturing a semiconductor device includes: providing a semiconductor substrate having a first side; forming a trench in the semiconductor...
2018/0151675 FIELD-EFFECT TRANSISTOR
A field-effect transistor includes a source electrode, a drain electrode, a semiconductor structure including a channel provided between the source electrode...
2018/0151674 III-V TRANSISTOR DEVICE WITH SELF-ALIGNED DOPED BOTTOM BARRIER
A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped...
2018/0151673 SUPERLATTICE MATERIALS AND APPLICATIONS
A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered...
2018/0151672 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel...
2018/0151671 SEMICONDUCTOR DEVICE HAVING ASYMMETRICAL SOURCE/DRAIN
A semiconductor device includes a substrate, an active fin protruding from the substrate, and an asymmetric diamond-shaped source/drain disposed on an upper...
2018/0151670 SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF
A semiconductor device includes a semiconductor substrate, a dielectric feature and an epitaxy feature. The epitaxy feature is on the semiconductor substrate....
2018/0151669 III-V SEMICONDUCTOR LAYERS, III-V SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a...
2018/0151668 ELECTRIC FIELD ASSISTED PLACEMENT OF NANOMATERIALS THROUGH DIELECTRIC ENGINEERING
A method of positioning nanomaterials that includes forming a set of electrodes on a substrate, and covering the electrodes and substrate with a single layer...
2018/0151667 METHOD FOR FORMING TRENCH STRUCTURE OF SEMICONDUCTOR DEVICE
A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable...
2018/0151666 METHOD OF FABRICATING METAL-INSULATOR-METAL CAPACITOR
A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including...
2018/0151665 SEMICONDUCTOR DEVICE AND LAYOUT METHOD
A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of...
2018/0151664 REDISTRIBUTION LAYER FOR SUBSTRATE CONTACTS
A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a...
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