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Patent # Description
2018/0151511 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF
A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first...
2018/0151510 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the...
2018/0151509 SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM
A semiconductor apparatus includes a chip ID generation unit, a chip ID transmission unit and a chip stack information generation unit. The chip ID generation...
2018/0151508 WAFER PROCESSING METHOD
A wafer processing method for processing a wafer has a front side and a back side, the front side of the wafer being formed with a plurality of crossing...
2018/0151507 Alignment Pattern for Package Singulation
A method includes forming an alignment pattern over an insulating layer formed over a carrier. A die is mounted over the carrier and encapsulated. Connectors...
2018/0151506 METAL LAYER INDEPENDENT VERSION IDENTIFIER
Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status...
2018/0151505 INTERCONNECTION STRUCTURES AND FABRICATION METHODS THEREOF
A method for fabricating an interconnection structure includes providing a substrate, forming a dielectric layer on the substrate, forming a conductive...
2018/0151504 SELF ALIGNED INTERCONNECT STRUCTURES
The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The...
2018/0151503 Interlevel Conductor Pre-Fill Utilizing Selective Barrier Deposition
A substrate is provided having a dual damascene structure formed within a dielectric material over the substrate. The dual damascene structure includes a...
2018/0151502 Fan-Out Package Having a Dummy Die and Method of Forming
A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The...
2018/0151501 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a first die; a first molding encapsulating the first die; a second die disposed over the first molding, and including a...
2018/0151500 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package...
2018/0151499 SEMICONDUCTOR PACKAGE STRUCTURE
Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via...
2018/0151498 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Package structures and methods for forming the package structures are provided. A package structure includes a molding compound having a surface. The package...
2018/0151497 THREE-DIMENSIONAL ARRAY DEVICE HAVING A METAL CONTAINING BARRIER AND METHOD OF MAKING THEREOF
A three-dimensional memory device includes driver transistors containing boron doped semiconductor active regions, device contact via structures in physical...
2018/0151496 POWER GRID STRUCTURES AND METHOD OF FORMING THE SAME
An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a...
2018/0151495 SEMICONDCUTOR DEVICE
A semiconductor device including an integrated circuit, a dielectric layer, a plurality of connecting terminals and at least one dummy conductor is provided....
2018/0151494 SEMICONDUCTOR DEVICE HAVING BURIED METAL LINE AND FABRICATION METHOD OF THE SAME
A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is...
2018/0151493 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A semiconductor device includes: a first conductive line disposed on a substrate, a second conductive line disposed on the substrate, and the second conductive...
2018/0151492 Device-Manufacturing Scheme for Increasing the Density of Metal Patterns in Inter-Layer Dielectrics
A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate...
2018/0151491 AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first...
2018/0151490 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower...
2018/0151489 METALLIC BLOCKING LAYER FOR RELIABLE INTERCONNECTS AND CONTACTS
A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A...
2018/0151488 INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a first dielectric layer on the...
2018/0151487 INTERCONNECT VIA WITH GROWN GRAPHITIC MATERIAL
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect...
2018/0151486 METHOD OF MANUFACTURING WIRING SUBSTRATE
A method of manufacturing a wiring substrate includes providing a support that includes a support substrate and first and second metal layers stacked in order...
2018/0151485 SEMICONDUCTOR DEVICE PACKAGE INCLUDING FILLING MOLD VIA
A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first...
2018/0151484 Pad Design for Reliability Enhancement in Packages
A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of...
2018/0151483 WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
A wiring board includes an insulating substrate that is rectangular in a plan view, a plurality of mount electrodes arranged to face each other on a first main...
2018/0151482 ELECTRONIC DEVICE, MANUFACTURING METHOD AND LEAD FRAME FOR SAME
An electronic device has a first surface providing electrical contact points and multiple side surfaces surrounding the first surface. The electronic device...
2018/0151481 Semiconductor Device Including a Bidirectional Switch
A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of...
2018/0151480 SEMICONDUCTOR DEVICE
A semiconductor device includes: a device main body that is annular or partially annular, the device main body having an inner circumferential surface formed...
2018/0151479 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a...
2018/0151478 SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device package includes an electronic device, a conductive frame and a first molding layer. The conductive frame is disposed over and...
2018/0151477 CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed...
2018/0151475 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, provided with a through hole which is surrounded by an...
2018/0151474 ON-CHIP THROUGH-BODY-VIA CAPACITORS AND TECHNIQUES FOR FORMING SAME
Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a...
2018/0151473 LIGHTWEIGHT LIQUID-COOLING-PLATE ASSEMBLY HAVING PLASTIC FRAME AND HEAT DISSIPATION SYSTEM USING SAME
The present invention relates to a lightweight liquid-cooling-plate assembly having a plastic frame and a heat dissipation system using the same. The...
2018/0151472 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor structure includes a die including a surface, a lid disposed over the surface of the die, and a thermally conductive material disposed between...
2018/0151471 HIGH THERMAL CONDUCTIVITY VIAS BY ADDITIVE PROCESSING
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect...
2018/0151470 INTEGRATED CIRCUIT NANOPARTICLE THERMAL ROUTING STRUCTURE IN INTERCONNECT REGION
An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The...
2018/0151469 SOLID-STATE DRIVE DEVICE
A solid-state drive device is provided. The solid-state drive device includes a housing, a first circuit board, and a second circuit board. The housing...
2018/0151468 DEVICE INTEGRATION OF ACTIVE COOLING SYSTEMS
In various embodiments, component-level and product-level devices incorporated one or more low-profile cooling devices for dissipating heat. The low-profile...
2018/0151467 SEMICONDCTOR DEVICE PACKAGE THERMAL CONDUIT
A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A...
2018/0151466 HEAT TRANSFER STRUCTURES AND METHODS FOR IC PACKAGES
A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package...
2018/0151465 SEMICONDUCTOR PACKAGE AND A METHOD OF MANUFACTURING THE SAME
A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval;...
2018/0151464 THERMAL ROUTING TRENCH BY ADDITIVE PROCESSING
An integrated circuit has a substrate which includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit...
2018/0151463 INTEGRATED CIRCUIT NANOPARTICLE THERMAL ROUTING STRUCTURE OVER INTERCONNECT REGION
An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower...
2018/0151462 INTEGRATED CIRCUIT SUBSTRATE AND METHOD OF PRODUCING THEREOF
An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace...
2018/0151461 STIFFENER FOR FAN-OUT WAFER LEVEL PACKAGING AND METHOD OF MANUFACTURING
Aspects of the present disclosure include a wafer level chip package and method of manufacture. The wafer level chip package includes one or more semiconductor...
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