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Patent # Description
2018/0151460 SEMICONDUCTOR DEVICE
A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to...
2018/0151459 SEMICONDUCTOR STRUCTURE, TESTING AND FABRICATING METHOD THEREOF
A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first...
2018/0151458 SEMICONDUCTOR STRUCTURE, TESTING AND FABRICATING METHODS THEREOF
A method of fabricating a semiconductor structure includes forming first and second features in a scribe region of a semiconductor substrate in which the first...
2018/0151457 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS
A semiconductor manufacturing method according to an embodiment includes forming a first film on a semiconductor substrate. The semiconductor manufacturing...
2018/0151456 METHOD AND SYSTEM FOR WET CHEMICAL BATH PROCESS
A method for performing a wet chemical process over a semiconductor wafer is provided. The method includes moving the semiconductor wafer into a chemical...
2018/0151455 THERMAL PROCESSING METHOD AND THERMAL PROCESSING APPARATUS THROUGH LIGHT IRRADIATION
A susceptor is preheated through light irradiation by a halogen lamp before the first semiconductor wafer of a lot as a processing target is transferred into a...
2018/0151454 METHOD FOR ADJUSTING ETCHING PARAMETERS
An etching method for an IC is provided. The etching method includes retrieving processing data including a pattern-density and at least one etching parameter...
2018/0151453 Semiconductor Device and Method
A semiconductor device and method includes forming a conductive post on a die; coupling a test probe to the conductive post with solder; and etching the solder...
2018/0151452 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Semiconductor device includes first and second nanowire structures disposed on semiconductor substrate extending in first direction on substrate. First...
2018/0151451 SRAM DEVICES AND FABRICATION METHODS THEREOF
A method for fabricating an SRAM device includes providing a base substrate including a pull up transistor (PUT) region and a pull down transistor (PDT)...
2018/0151450 Multi-Gate Device and Method of Fabrication Thereof
A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region...
2018/0151449 SEMICONDUCTOR STRUCTURE INCLUDING TWO-DIMENSIONAL AND THREE-DIMENSIONAL BONDING MATERIALS
One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from...
2018/0151448 BREAKDOWN RESISTANT SEMICONDUCTOR APPARATUS AND METHOD OF MAKING SAME
A semiconductor device includes a substrate, a first transistor on the substrate, and a second transistor on the substrate. The first transistor has a first...
2018/0151447 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal...
2018/0151446 FINFET DEVICES AND METHODS OF FORMING THE SAME
A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing...
2018/0151445 FORMING A PROTECTIVE LAYER TO PREVENT FORMATION OF LEAKAGE PATHS
A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask located over the gate electrode. The hard mask...
2018/0151444 ARRAY SUBSTRATE AND MANUFACTURING METHOD FOR THE SAME
An array substrate and a manufacturing method. The method includes: patterning the first metal layer through a first mask to form a gate electrode and a first...
2018/0151443 METHODS FOR FORMING THE ISOLATION STRUCTURE OF THE SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES
A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area...
2018/0151442 Semiconductor Device and Method of Manufacture
A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to...
2018/0151441 Semiconductor Device and Method
In an embodiment, a method includes: patterning a plurality of mandrels over a mask layer; forming an etch coating layer on top surfaces of the mask layer and...
2018/0151440 FinFET Device and Method of Forming Same
A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the...
2018/0151439 Asymmetric Source/Drain Epitaxy
A method includes forming a plurality of fins on a substrate and a dummy gate structure over the fins. A spacer layer is formed over the dummy gate structure...
2018/0151438 THRESHOLD VOLTAGE ADJUSTMENT FOR A GATE-ALL-AROUND SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second...
2018/0151437 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction...
2018/0151436 DIRECT BONDING METHOD
The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second...
2018/0151435 METHOD AND APPARATUS FOR PLASMA DICING A SEMI-CONDUCTOR WAFER
The present invention provides a method for plasma dicing a substrate. The substrate is provided with a top surface and a bottom surface, the top surface of...
2018/0151434 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION
There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a...
2018/0151433 GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
2018/0151432 Self Aligned Via and Method for Fabricating the Same
A self aligned via and a method for fabricated a semiconductor device using a double-trench constrained self alignment process to form the via. The method...
2018/0151431 MEMORY DEVICE AND OPERATION METHOD THEREOF
A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a...
2018/0151430 METHOD OF FORMING SUPERCONDUCTOR STRUCTURES
A method of forming a superconductor structure is provided. The method comprises forming a superconducting element in a first dielectric layer that has a top...
2018/0151429 Methods for Forming Metal Layers in Openings and Apparatus for Forming Same
A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are...
2018/0151428 CONDUCTIVE STRUCTURE AND METHOD FOR MANUFACTURING CONDUCTIVE STRUCTURE
A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a...
2018/0151427 Method of Cleaning Wafer After CMP
A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material...
2018/0151426 METHOD OF FLAT CU FORMING WITH PARTIAL CU PLATING
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate,...
2018/0151425 Contact Openings and Methods Forming Same
A method includes performing an implantation on a portion of a first layer to form an implanted region, and removing un-implanted portions of the first layer....
2018/0151424 METHODS TO FILL HIGH ASPECT RATIO FEATURES ON SEMICONDUCTOR SUBSTRATES WITH MOCVD COBALT FILM
In some embodiments, a method of forming a cobalt layer on a substrate disposed in a process chamber, includes: (a) exposing the substrate to a first process...
2018/0151423 THE USE OF NOBLE METALS IN THE FORMATION OF CONDUCTIVE CONNECTORS
In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed...
2018/0151422 Method of Forming Interconnect Structures
A method includes forming a first conductive feature in a first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second...
2018/0151421 Semiconductor Device and Method
A semiconductor device and method of manufacture comprise placing an etch stop layer of a material such as aluminum oxide over a conductive element, placing a...
2018/0151420 INTERCONNECT STRUCTURE
Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric...
2018/0151419 METHOD OF FORMING A DEVICE HAVING A DOPING LAYER AND DEVICE FORMED
A method of making a device includes forming an opening in a dielectric layer to expose a conductive region in a substrate. The method further includes...
2018/0151418 PATTERN FORMING METHOD AND IMPRINT APPARATUS
A pattern forming method includes forming a first resist pattern on a substrate using imprint lithography. And forming a resist onto the substrate at least at...
2018/0151417 METHOD OF FORMING SEMICONDUCTOR DEVICE
A method for forming a semiconductor device includes the following steps. An IMD layer is provided on a substrate. A plurality of block patterns is formed on...
2018/0151416 2-D INTERCONNECTIONS FOR INTEGRATED CIRCUITS
Two-dimensional (2-D) interconnects in a one-dimensional (1-D) patterning layout for integrated circuits is disclosed. This disclosure provides methods of...
2018/0151415 FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES
Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks...
2018/0151414 SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME
A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation...
2018/0151413 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR
A method of fabricating a semiconductor structure. The method includes forming a sacrificial gate structure, depositing a dielectric material, and implanting...
2018/0151412 SEMICONDUCTOR STRUCTURE AND PLANARIZATION METHOD THEREOF
A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and...
2018/0151411 INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT
An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a...
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