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Patent # Description
2018/0151258 Motor Training
A method for motor training comprising: receiving from one or more sensors an orientation of a head mounted display of the subject; adapting a base video...
2018/0151257 System, Apparatus, and Method for Dispensary Management
A computerized dispensary management system and method enhances dispensary product management and are supported by a blister pack separation apparatus. The...
2018/0151256 Pharmacy Dispensing System and Method
A system for filling a prescription order for a patient includes a plurality of trays each having an RFID tag for storing a unique identifier corresponding to...
2018/0151255 REMOTE MONITORING OF MEDICAL DEVICES
Methods and systems for calibrating billing cycles for remote monitoring patients and categorizing medical device interrogation data received from remotely...
2018/0151254 HIGH-SPEED SIMILAR CASE SEARCH METHOD AND DEVICE THROUGH REDUCTION OF LARGE SCALE MULTI-DIMENSIONAL TIME SERIES...
Provided are a search method and device for searching for a case similar to user's health data at high-speed from large scale multi-dimensional time series...
2018/0151253 ACCELERATED CLINICAL TRIAL DESIGN AND RECRUITMENT
Accelerated clinical trial design and recruitment is disclosed. In an example, participants and clinical research sites are pre-identified and prequalified for...
2018/0151252 METHOD AND APPARATUS FOR A VIRTUAL CLINICAL TRIAL SELF-RECRUITMENT MARKETPLACE FOR PATIENTS BASED ON BEHAVIORAL...
Method, Apparatus and non-transitory computer readable media that enhance patient-recruitment and participation in clinical trials preferably includes...
2018/0151251 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system may include: a memory device including a plurality of memory blocks configured in a plurality of super memory blocks; and a controller suitable...
2018/0151250 MEMORY DEVICE
A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information...
2018/0151249 DATA STORAGE APPARATUS AND OPERATING METHOD THEREOF
A data storage apparatus includes a nonvolatile memory device and a controller configured to determine whether or not one or more addresses of defective bit...
2018/0151248 TESTING CONTENT ADDRESSABLE MEMORY AND RANDOM ACCESS MEMORY
The present invention provides a system and method of testing CAMs and RAMs. In an exemplary embodiment, the system includes a multiple input signature...
2018/0151247 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED SYSTEM
A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. The semiconductor device that mounts a plurality of...
2018/0151246 BUILT-IN SELF-TEST FOR EMBEDDED SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY
Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example...
2018/0151245 HAMMING-DISTANCE ANALYZER
A device is disclosed that includes a memory array, a comparing circuit, and a calculating circuit. The memory array is configured to store a first response of...
2018/0151244 MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
A memory circuit may include a plurality of electrically programmable memory cells arranged in a non-volatile memory cell array along a rows and columns, a...
2018/0151242 SAMPLE AND HOLD CIRCUIT
A sample and hold circuit including a charge path coupled to a voltage source. A first node of the charge path is located closer to the voltage source in the...
2018/0151241 SHIFT REGISTER UNIT, SHIFT REGISTER, GATE DRIVING CIRCUIT AND DISPLAY DEVICE
A shift register unit, a shift register, a gate driving circuit and a display device are discloses. The shift register unit has an output node Out(n) of a...
2018/0151240 ACCIDENTAL FUSE PROGRAMMING PROTECTION CIRCUITS
Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a...
2018/0151239 Word Line Driver
A word line driver comprising a select word line level shifter configured to generate at least one output signal in the first voltage domain or a second...
2018/0151238 NOVEL OTPROM FOR POST-PROCESS PROGRAMMING USING SELECTIVE BREAKDOWN
At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data...
2018/0151237 OPERATION METHOD OF A NONVOLATILE MEMORY DEVICE FOR CONTROLLING A RESUME OPERATION
An operation method of a nonvolatile memory device for programming memory cells connected to a selected word line, the method including: performing a program...
2018/0151236 NONVOLATILE MEMORY DEVICE GENERATING LOOP STATUS INFORMATION, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING...
A nonvolatile memory device includes a cell array comprising memory cells; a voltage generator that provides a program or verification voltage to a word line...
2018/0151235 SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SAME
A semiconductor device according to an embodiment includes first and second memory cells, a first word line, and first and second bit lines. The first memory...
2018/0151234 NONVOLATILE MEMORY DEVICE FOR PERFORMING A PARTIAL READ OPERATION AND A METHOD OF READING THE SAME
A nonvolatile memory device includes a first cell string including a first dummy cell and connected to a selected string select line, a second cell string...
2018/0151233 SENSE AMPLIFIER CIRCUIT
Provided is a sense amplifier circuit for detecting data having been read from a memory cell. The sense amplifier circuit includes: a potential control unit...
2018/0151232 MEMORY CONTROL CIRCUIT AND METHOD THEREOF
This invention discloses a memory control circuit and a method thereof. The memory control method includes the steps of: transmitting a first clock to a serial...
2018/0151231 METHOD FOR REDUCING A MEMORY OPERATION TIME IN A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING NON-VOLATILE...
A method can be used for reducing a memory operation time in a non-volatile memory device having a memory array with a number of memory cells. The method...
2018/0151230 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a voltage generator suitable for applying an erase voltage...
2018/0151229 SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication...
2018/0151228 SEMICONDUCTOR DEVICE
A semiconductor device includes a memory unit and a control unit which controls the memory unit. The memory unit a memory which is configured with a...
2018/0151227 Failure Detection Circuitry for Address Decoder for a Data Storage Device
A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device...
2018/0151226 MEMORY CELL
A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit...
2018/0151225 SEMICONDUCTOR INTEGRATED CIRCUIT
An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a...
2018/0151224 RRAM-BASED AUTHENTICATION CIRCUIT
A memory device includes a memory array comprising a plurality of bits, wherein each bit comprises two memory cells each having a variable resistance; a...
2018/0151223 PHASE-CHANGE MEMORY DEVICE WITH DRIVE CIRCUIT
A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a...
2018/0151222 SOFT INFORMATION MODULE
A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or...
2018/0151221 SERIALIZED SRAM ACCESS TO REDUCE CONGESTION
A circuit includes a serializer configured to receive a non-serialized input signal having a first bit-width and generate a plurality of serialized input...
2018/0151220 GENERATING A COLLAPSED VDD USING A WRITE-ASSIST COLUMN TO DECREASE A WRITE VOLTAGE
A write-assist cell includes a first pull-up transistor electrically coupled to a voltage array and a first node, a first pass-gate transistor electrically...
2018/0151219 MEMORY DEVICE WITH DETERMINED TIME WINDOW
A memory device includes a memory array that comprises at least a bit cell configured to store a data bit; a tracking circuit, coupled to the memory array, and...
2018/0151218 METHOD OF OPERATING MEMORY DEVICE AND METHOD OF OPERATING MEMORY SYSTEM
A method of operating a memory device, a first setting signal is received by a first memory device among a plurality of memory devices. The first memory device...
2018/0151217 SEMICONDUCTOR DEVICE
A semiconductor device may be provided. The semiconductor device may include a data input and output circuit (I/O) configured to selectively or simultaneously...
2018/0151216 CIRCUIT FOR GENERATING PERIODIC SIGNAL AND MEMORY DEVICE INCLUDING SAME
Provided is a periodic signal generation circuit including a clock generation unit suitable for generating first to N.sup.th clocks which have a basic period...
2018/0151215 Dynamic Memory Supporting Simultaneous Refresh and Data-Access Transactions
Described are dynamic memory systems that perform overlapping refresh and data access (read or write) transactions that minimize the impact of the refresh...
2018/0151214 NON-COLLINEAR MAGNETORESISTIVE DEVICE
A non-collinear magnetoresistive device, includes: a free layer; a fixed layer; and a non-magnetic layer disposed between the free layer and the fixed layer,...
2018/0151213 Magnetic Tunnel Junction Memory Device
Various memory devices and associated methods of operation are disclosed herein. An exemplary method includes flowing a current through an electrode of a...
2018/0151212 MAGNETIC MEMORY DEVICE AND METHOD OF WRITING MAGNETIC MEMORY DEVICE
Embodiments provide a magnetic memory device and a method of writing a magnetic memory device. The magnetic memory device includes a magnetic tunnel junction...
2018/0151211 Memory Device with a Low-Current Reference Circuit
A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is...
2018/0151210 SHARED SOURCE LINE ARCHITECTURES OF PERPENDICULAR HYBRID SPIN-TORQUE TRANSFER (STT) AND SPIN-ORBIT TORQUE (SOT)...
The present disclosure relates to a hybrid spin-transfer torque (STT) and spin-bit torque (SOT) magnetic random access memory (MRAM). The cells of the hybrid...
2018/0151209 MAGNETIC MEMORY DEVICE AND METHOD OF WRITING MAGNETIC MEMORY DEVICE
Embodiments provide a magnetic memory device and a method of writing a magnetic memory device. The magnetic memory device includes a magnetic tunnel junction...
2018/0151208 SEMICONDUCTOR SYSTEM
A semiconductor system may include a controller and a semiconductor memory device. The controller may provide an external command, an external address and a...
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