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Patent # Description
2018/0158534 MEMORY CIRCUIT AND METHOD OF OPERATING A MEMORY CIRCUIT
In various embodiments, a memory circuit is provided. The memory circuit may include a plurality of electrically programmable memory cells arranged in an...
2018/0158533 APPARATUS AND METHODS FOR PROTECTION AGAINST INADVERTENT PROGRAMMING OF FUSE CELLS
Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a...
2018/0158532 PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME
The present disclosure relates to a method of a non-volatile one time programmable memory (OTPM) including parallel programming of all banks of the OTPM by...
2018/0158531 Pulsed Control Line Biasing In Memory
In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be...
2018/0158530 METHOD FOR DETECTING A THINNING OF THE SEMICONDUCTOR SUBSTRATE OF AN INTEGRATED CIRCUIT FROM ITS BACK FACE AND...
The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of...
2018/0158529 MULTIPLE BLOCKS PER STRING IN 3D NAND MEMORY
Embodiments describe techniques and configurations for an apparatus including a three-dimensional (3D) memory array having a plurality of strings of memory...
2018/0158528 CONTROL LOGIC, SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF OPERATING THE SAME
Provided herein may be a control logic, semiconductor memory device, method of operating the control logic, and or method of operating the semiconductor memory...
2018/0158527 VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS
In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for...
2018/0158526 INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING SAME
An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on...
2018/0158525 RESISTANCE CHANGE TYPE MEMORY
According to one embodiment, a resistance change type memory includes: a variable resistance element connected between first and second bit lines; a write...
2018/0158524 NON-VOLATILE MEMORY APPARATUS INCLUDING VOLTAGE CLAMPING CIRCUIT
A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit...
2018/0158523 ELECTRONIC DEVICE
An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically...
2018/0158522 MULTIPORT MEMORY, MEMORY MACRO AND SEMICONDUCTOR DEVICE
A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a...
2018/0158521 SRAM CELL WITH DYNAMIC SPLIT GROUND AND SPLIT WORDLINE
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor...
2018/0158520 COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive...
2018/0158519 COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING THE MEMORY CELLS FOR XOR AND XNOR COMPUTATIONS
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive...
2018/0158518 COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING MEMORY CELLS
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND,...
2018/0158517 COMPUTATIONAL MEMORY CELL AND PROCESSING ARRAY DEVICE USING MEMORY CELLS
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND,...
2018/0158516 STATIC RANDOM ACCESS MEMORY DEVICE HAVING UNIFORM WRITE CHARACTERISTICS
A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage...
2018/0158515 TERNARY SENSE AMPLIFIER AND SRAM ARRAY REALIZED BY THE TERNARY SENSE AMPLIFIER
A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1.sup.st CNFET...
2018/0158514 LIMITING BITLINE PRECHARGE DRIVE FIGHT CURRENT USING MULTIPLE POWER DOMAINS
A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing...
2018/0158513 SEMICONDUCTOR DEVICE
The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit...
2018/0158512 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WEARABLE DEVICE
To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a...
2018/0158511 SEMICONDUCTOR MEMORY DEVICE
When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage...
2018/0158510 SRAM CELL FOR INTERLEAVED WORDLINE SCHEME
Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in...
2018/0158509 SEMICONDUCTOR DEVICE
A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and...
2018/0158508 MEMORY DEVICE INCLUDING VOLATILE MEMORY, NONVOLATILE MEMORY AND CONTROLLER
According to one embodiment, a memory device is connectable to a host, and includes a nonvolatile memory, a volatile memory which is used as a cache of the...
2018/0158507 MEMORY DEVICE AND MEMORY SYSTEM PERFORMING A HAMMER REFRESH OPERATION AND ASSOCIATED OPERATIONS
A memory system includes a memory controller and a memory device. The memory controller determines and provides a hammer address. The hammer address is an...
2018/0158506 PULSE-STRETCHER CLOCK GENERATOR CIRCUIT FOR HIGH SPEED MEMORY SUBSYSTEMS
The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured...
2018/0158505 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
Provided herein is a semiconductor memory device and a method for operating the same. The semiconductor memory device may include a memory cell array including...
2018/0158504 APPARATUSES AND METHODS FOR CONTROLLING REFRESH OPERATIONS
An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit...
2018/0158503 CONTROL UNIT HAVING RADIO INTERFERENCE AVOIDING FUNCTION
A control unit includes a non-volatile memory and a CPU. The non-volatile memory stores activation interval information indicating an activation interval of...
2018/0158502 DYNAMIC REFERENCE VOLTAGE DETERMINATION
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a...
2018/0158501 DYNAMIC ADJUSTMENT OF MEMORY CELL DIGIT LINE CAPACITANCE
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
2018/0158500 NON-VOLATILE MEMORY CIRCUIT
The present technique relates to a non-volatile memory circuit ensuring a small size and low power consumption while maintaining stable write. A slave latch is...
2018/0158499 MAGNETIC MEMORY
A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically...
2018/0158498 MAGNETORESISTIVE DEVICES AND METHODS THEREFOR
The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more...
2018/0158497 MAGNETIC DEVICE CONFIGURED TO PERFORM AN ANALOG ADDER CIRCUIT FUNCTION AND METHOD FOR OPERATING SUCH MAGNETIC...
A magnetic device configured to perform an analog adder circuit function and including a plurality of magnetic units. Each magnetic unit includes n magnetic...
2018/0158496 MAGNETORESISTIVE ELEMENT AND MEMORY CIRCUIT
A magnetoresistive element includes: a free layer that includes a magnetostrictive layer containing a magnetostrictive material; a pin layer that includes a...
2018/0158495 ZQ CALIBRATION METHOD OF MEMORY DEVICE WITH SHARED ZQ PIN AND MEMORY DEVICE PERFORMING THE ZQ CALIBRATION METHOD
A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first...
2018/0158494 SEMICONDUCTOR MEMORY DEVICES, METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS
A semiconductor memory device includes bank arrays, row decoders, column decoders, a timing control circuit and repeaters. The bank arrays are distributed in a...
2018/0158493 APPARATUS AND METHOD FOR CONTROLLING MEMORY DEVICE
An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for...
2018/0158492 STORAGE DEVICE OPERATING DIFFERENTLY ACCORDING TO TEMPERATURE OF MEMORY
A storage device includes memories and a controller. The controller controls first and second program operations on the memory. When a temperature of the...
2018/0158491 Forwarding Signal Supply Voltage in Data Transmission System
In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first...
2018/0158490 MEMORY ARRANGEMENT
A memory arrangement and method to arrange memories are disclosed. The memory arrangement comprises at least two memory chips (M1, M2) arranged on a Printed...
2018/0158489 SYSTEM AND METHODS FOR PROVIDING USER GENERATED VIDEO REVIEWS
Methods and systems for content aggregation and distribution are described. Video content may be received from a plurality of sources. The video content may be...
2018/0158488 CONTINUOUS AUTOMATED SYNCHRONIZATION OF AN AUDIO TRACK IN A MOVIE THEATER
A method for the continuous automated audio synchronization of an alternative audio track with the playback of the combined audio and video of a motion picture...
2018/0158487 IMAGING DEVICE AND PLAYBACK DEVICE
An imaging device includes an imaging element that acquires a first image based on signal charge generated during a first accumulation time, and a second image...
2018/0158486 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DISTRIBUTED VIDEO EDITING
A network editor comprises a central location with stored videos such as movies that can be edited by editors at remote locations. An editor receives a...
2018/0158485 Creation of Media Clips from Media Broadcasts
According to some implementations of the present disclosure, computer-implemented methods and systems for generating media clips are disclosed. According to...
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