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Patent # Description
2018/0157625 METHOD, SYSTEM AND APPARATUS FOR DISPLAYING AN ELECTRONIC DOCUMENT
A method of displaying an electronic document. A list of glyphs in an electronic document specified with a font is determined, the electronic document being...
2018/0157624 ELECTRONIC FORM SYSTEM AND METHOD FOR EDITTING FORM THEREOF
Disclosed is an electronic form system capable for transforming directly a form format of the existing document processing software to a form editor of the...
2018/0157623 SENSING DATA BASED ESTIMATION METHOD AND SENSING DATA BASED ESTIMATION SYSTEM
A sensing data based estimation method is applied to an estimation system, and the estimation system includes a sensor, a storage and a processor. The...
2018/0157622 METHOD FOR CONSTRUCTING A CIRCUIT FOR FAST MATRIX-VECTOR MULTIPLICATION
A circuit for fast matrix-vector multiplication and a method for constructing that circuit are provided, comprising processing a matrix to obtain a pair...
2018/0157621 FOUR STEPS ASSOCIATIVE FULL ADDER
A method to add a first one bit variable with a second one bit variable and a carry-in bit, to generate a sum bit and a carry-out bit, the method includes...
2018/0157620 COMPUTER-IMPLEMENTED SYSTEMS AND METHODS FOR TIME SERIES EXPLORATION
Systems and methods are provided for analyzing unstructured time stamped data. A distribution of time-stamped data is analyzed to identify a plurality of...
2018/0157619 COMPUTER-IMPLEMENTED SYSTEMS AND METHODS FOR TIME SERIES EXPLORATION
Systems and methods are provided for analyzing unstructured time stamped data. A distribution of time-stamped data is analyzed to identify a plurality of...
2018/0157618 Integration Pattern Implementations Using Reconfigurable Logic Devices
Example embodiments of the present disclosure include an integration system comprising a machine-readable medium (e.g., a memory) and a reconfigurable logic...
2018/0157617 ELECTRONIC APPARATUS, IMAGE FORMING APPARATUS, AND CONTROL METHOD AND PROGRAM THEREFOR
An electronic apparatus includes a first processor and a second processor. The first processor includes a detection unit to detect output of an internal-reset...
2018/0157616 CLOCK GATING CIRCUIT
A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an...
2018/0157615 FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY
An integrated circuit device includes a transmitter circuit including an output driver. The integrated circuit device includes a first register to store a...
2018/0157614 SCALABLE DIRECT INTER-NODE COMMUNICATION OVER PERIPHERAL COMPONENT INTERCONNECT-EXPRESS (PCIe)
A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted...
2018/0157613 VALUE DOCUMENT HANDLING APPARATUS HAVING A DATA COMMUNICATION SYSTEM AND METHOD FOR DISTRIBUTING SENSOR DATA IN...
Methods involve distributing a data stream in a value-document processing apparatus from at least one sensor to at least one processing unit as well as a...
2018/0157612 SERVER
A server includes a main board, a bridge board and sub boards. The bridge board is electrically connected to the main board and the sub boards. The main board...
2018/0157611 CAMERA CONTROL INTERFACE SLAVE DEVICE TO SLAVE DEVICE COMMUNICATION
In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave...
2018/0157610 MOBILE HARDWARE FOB WITH DEVICE ECOSYSTEM FOR MODULAR I/O EXTENSION DEVICES
A fob device includes a portable housing below a size needed to accommodate an input/output component for providing access to a functionality of the fob device...
2018/0157609 CONTROLLER-PHY CONNECTION USING INTRA-CHIP SERDES
An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface....
2018/0157608 CONNECTING DEVICE AND TRANSMITTING SYSTEM USING THE SAME
A connecting device able to allocate master and slave roles between two intelligent devices having On-The-Go functions, depending on the intelligent device...
2018/0157607 METHOD AND SYSTEM FOR BUFFER STATE BASED LOW POWER OPERATION IN A MOCA NETWORK
A first device of a Multimedia Over Coax Alliance (MoCA) network may communicate with a second device of the MoCA network to control power-save operation of...
2018/0157606 SYSTEM AND METHOD FOR MEMORY ACCESS TOKEN REASSIGNMENT
A network device is described. The network device includes a plurality of ingress interfaces, a plurality of memory units configured to store packets received...
2018/0157605 CONFIGURATION OF A MEMORY CONTROLLER FOR COPY-ON-WRITE
Examples include configuration of a memory controller for copy-on-write. Some examples include, in response to a determination to take a snapshot of memory...
2018/0157604 Scripted Arbitration Circuit
This patent application relates generally to a scripted arbiter in which arbitration processing is controlled through a script executed by the arbiter, where...
2018/0157603 DYNAMIC CONFIGURATION AND PERIPHERAL ACCESS IN A PROCESSOR
In various implementations, a system includes a memory, a processor, and an execution-aware memory protection unit (EA-MPU). The EA-MPU is configured to...
2018/0157602 OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING ADAPTIVE PREFETCH CONTROL
Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: determining, by a...
2018/0157601 APPARATUS AND METHOD FOR AVOIDING CONFLICTING ENTRIES IN A STORAGE STRUCTURE
An apparatus and method are provided for avoiding conflicting entries in a storage structure. The apparatus comprises a storage structure having a plurality of...
2018/0157600 TRANSMITTING CONTENTS OF AN OPERATION FIELD TO A MEDIA CONTROLLER
In example implementations, mapping fields and respective operation fields may be stored in a translation lookaside buffer (TLB) of a central processing unit...
2018/0157599 TRANSLATION LOOKASIDE BUFFER SWITCH BANK
Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a...
2018/0157598 APPARATUSES, METHODS, AND SYSTEMS TO SHARE TRANSLATION LOOKASIDE BUFFER ENTRIES
Methods, systems, and apparatuses relating to sharing translation lookaside buffer entries are described. In one embodiment, a processor includes one or more...
2018/0157597 DDR STORAGE ADAPTER
A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range...
2018/0157596 Trapless Shadow Page Tables
Techniques for implementing trapless shadow page tables in a virtualized host system are provided. In one embodiment, an SPT accelerator device of the host...
2018/0157595 OPTIMIZING MEMORY MAPPING(S) ASSOCIATED WITH NETWORK NODES
Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second...
2018/0157594 USING CACHE LISTS FOR PROCESSORS TO DETERMINE TRACKS TO DEMOTE FROM A CACHE
Provided are a computer program product, system, and method for using cache lists for processors to determine tracks in a storage to demote from a cache....
2018/0157592 DISTRIBUTION AND EXECUTION OF INSTRUCTIONS IN A DISTRIBUTED COMPUTING ENVIRONMENT
Methods and apparatus for distribution and execution of instructions in a distributed computing environment are disclosed. An example method includes...
2018/0157591 Instruction and Logic for Software Hints to Improve Hardware Prefetcher Effectiveness
Embodiments provide for a processor comprising a cache, a prefetcher to select information according to a prefetcher algorithm and to send the selected...
2018/0157590 FILTERING COHERENCY PROTOCOL TRANSACTIONS
A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an...
2018/0157589 PROACTIVE CACHE COHERENCE
A distributed shared-memory system includes several nodes that each have one or more processor cores, caches, local main memory, and a directory. Each node...
2018/0157588 ADDRESSING SCHEME FOR DISTRIBUTED HARDWARE STRUCTURES
Embodiments of the present invention provide an apparatus having a plurality of selectable entities having associated physical addresses, wherein the...
2018/0157587 RANDOMLY WRITABLE MEMORY DEVICE AND METHOD OF OPERATING THEREOF
A method of writing data to a DNA strand comprises cutting an address block of a selected address-data block unit of the DNA strand to form first and second...
2018/0157586 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a memory device including a plurality of memory regions; and a controller suitable for selecting one or more candidate memory...
2018/0157585 MEMORY ALLOCATION ON NON-VOLATILE STORAGE
Techniques for allocating memory on non-volatile storage mediums, rather than on RAM storage mediums, are provided. In some embodiments, first functions in...
2018/0157584 IMPLICIT COORDINATION OF DEPLOYMENT AND REGRESSION TESTING ACROSS DATA CENTERS AND SYSTEM CLUSTERS
The disclosed methods and systems for coordinating deployment and regression testing across data centers and system clusters in multiple service clouds include...
2018/0157583 APPLICATION TESTING ON A BLOCKCHAIN
A blockchain test configuration may provide a simple and secure infrastructure for testing applications. One example method of operation may comprise one or...
2018/0157582 AUTOMATED TEST RUNS IN AN INTEGRATED DEVELOPMENT ENVIRONMENT SYSTEM AND METHOD
A method, computer program product, and computer system for editing code, by a computing device, via an integrated development environment. The code is...
2018/0157581 AUTOMATED SYSTEM TESTING IN A COMPLEX SOFTWARE ENVIRONMENT
Method and system are provided for automated system testing in a complex software environment. The method includes: collecting data during a test run of a...
2018/0157580 DEBUG SESSION ANALYSIS FOR RELATED WORK ITEM DISCOVERY
A method for automatic debug session analysis for related work item discovery, is provided. The method includes recording metadata describing a particular...
2018/0157579 DIFFERENCING OF EXECUTABLE DATAFLOW GRAPHS
A method for displaying differences between a first executable dataflow graph and a second executable dataflow graph includes comparing a specification of the...
2018/0157578 ISSUANCE OF STATIC ANALYSIS COMPLAINTS
Embodiments include methods, systems, and computer program products for using static analysis to issue complaints. Aspects include generating, using a...
2018/0157577 OBJECTIVE EVALUATION OF CODE BASED ON USAGE
A method, associated system, and computer program product are disclosed for facilitating improved objectivity of feedback for evaluating software programs. The...
2018/0157576 Partial Process Recording
Techniques for processing recorded program data are described. In implementations, a trace module in a computing device processes instructions of a recorded...
2018/0157575 MONITORING THE OPERATION OF A PROCESSOR
Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent...
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