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Patent # Description
2018/0166419 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first device; a second device laterally adjacent to the first device; a molding member encapsulating the first device and...
2018/0166418 METHOD FOR PREPARING A WAFER LEVEL CHIP-ON-CHIP SEMICONDUCTOR STRUCTURE
A method for preparing a wafer level chip-on-chip semiconductor structure. The semiconductor structure includes a first semiconductor device; at least one...
2018/0166416 Method for Transferring and Placing a Semiconductor Device on a Substrate
An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor...
2018/0166415 Method for Die and Clip Attachment
A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a...
2018/0166414 SEMICONDUCTOR PACKAGE HAVING MULTI-TIER BONDING WIRES AND COMPONENTS DIRECTLY MOUNTED ON THE MULTI-TIER BONDING...
A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires...
2018/0166413 ELECTRICALLY CONDUCTIVE BOND BETWEEN AT LEAST TWO ELECTRICAL COMPONENTS AT A CARRIER MOUNTED WITH ELECTRONIC...
The invention relates to the electrically conductive bond between at least two electrical components and/or devices at a carrier mounted with electronic and/or...
2018/0166412 SEMICONDUCTOR MODULE
A semiconductor module that restrains the occurrence of detachment and an operation failure. The semiconductor module includes a PCB base, a conductive die pad...
2018/0166411 MOUNT STRUCTURE
A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer...
2018/0166410 POWER MODULE ASSEMBLY WITH DUAL SUBSTRATES AND REDUCED INDUCTANCE
A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current...
2018/0166409 Conductive External Connector Structure and Method of Forming
External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical...
2018/0166408 Bond Structures and the Methods of Forming the Same
A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first...
2018/0166407 SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS
Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least...
2018/0166406 SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYER AND METHOD OF MAKING THE SAME
A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further...
2018/0166405 STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH ANTENNA ELEMENT
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first...
2018/0166404 WIRELESS PACKAGE AND FABRICATION METHOD THEREOF
A wireless package includes a package substrate, a RFIC chip, a resilient connector, a molding compound encapsulating the RFIC chip, the resilient connector,...
2018/0166403 METHODS, CIRCUITS AND SYSTEMS FOR A PACKAGE STRUCTURE HAVING WIRELESS LATERAL CONNECTIONS
A packaged semiconductor device includes an insulating material forming a side surface of the packaged semiconductor device. An integrated-circuit chip is...
2018/0166402 INTEGRATED EFUSE
A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A...
2018/0166401 SEMICONDUCTOR DEVICE
The present disclosure provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of...
2018/0166400 TERNARY PUF UNIT AND CIRCUIT REALIZED BY CNFET
The present invention discloses a ternary PUF unit and circuit realized by CNFET; the ternary PUF circuit comprises a ternary row decoder, a ternary column...
2018/0166399 LAYOUT-DRIVEN METHOD TO ASSESS VULNERABILITY OF ICS TO MICROPROBING ATTACKS
A method of assessing vulnerability of Integrated Circuit (IC) can include: preparing a list of logic nets of the IC; obtaining rectangular segments from the...
2018/0166398 CORE-SHELL PARTICLES FOR ANTI-TAMPERING APPLICATIONS
Devices and methods for resisting or preventing physical tampering of electronic components are described. A tamper resistant apparatus comprises a tampering...
2018/0166397 SEMICONDUCTOR DEVICE
A semiconductor device includes: an upper-surface electrode on an upper surface of a semiconductor element; a plated layer on an upper surface of the...
2018/0166396 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also...
2018/0166395 SEMICONDUCTOR STRUCTURE, INTEGRATED CIRCUIT DEVICE, AND METHOD OF FORMING SEMICONDUCTOR STRUCTURE
A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor...
2018/0166394 HIGH-FREQUENCY MODULE AND MANUFACTURING METHOD THEREFOR
The present disclosure improves the adhesive strength of a shield film in a high-frequency module that includes a shield film that shields components from...
2018/0166393 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
2018/0166392 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator over a substrate; an...
2018/0166391 INTERCONNECT STRUCTURE HAVING A GRAPHENE LAYER
An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the...
2018/0166390 PLANAR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Provided is a planar package structure and its manufacturing method. The planar package structure totally packages a die to make the die unexposed and to...
2018/0166389 Semiconductor Device
A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The...
2018/0166388 SEMICONDUCTOR SUSBTRATE WITH ELECTRICALLY ISOLATING DIELECTRIC PARTITION
A semiconductor device and a method of making the same. The device includes a substrate comprising a major surface and a backside. The device also includes a...
2018/0166387 TRANSMIT-AND-RECEIVE MODULE
A transmit-and-receive module includes a wiring substrate, a low-noise amplifier, a power amplifier, an insulating resin, and a conductive shield. The wiring...
2018/0166386 POWER GRID, IC AND PLACEMENT METHOD FOR POWER GRID
A power grid of an integrated circuit (IC) is provided. The power grid includes a plurality of first power lines formed in a first metal layer, a plurality of...
2018/0166385 INTERCONNECT STRUCTURE AND METHOD OF FORMING THE SAME
Aspects of the present disclosure include a method for forming a contact on a semiconductor device, the semiconductor device including a conductive region...
2018/0166384 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over...
2018/0166383 AIRGAPS TO ISOLATE METALLIZATION FEATURES
The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The...
2018/0166382 ANTI-FUSE DEVICE AND MEMORY DEVICE INCLUDING THE SAME
An anti-fuse device includes a program transistor and a read transistor. The program transistor executes a program via insulation breakdown of a gate...
2018/0166381 THROUGH-SILICON VIA WITH IMPROVED SUBSTRATE CONTACT FOR REDUCED THROUGH-SILICON VIA (TSV) CAPACITANCE VARIABILITY
The present disclosure relates to semiconductor structures and, more particularly, to Through-Silicon Via (TSV) structures with improved substrate contact and...
2018/0166380 VERTICAL SEMICONDUCTOR DEVICE
A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a...
2018/0166379 REPLACEMENT CONTACTS
The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first...
2018/0166378 PACKAGED SEMICONDUCTOR DEVICES WITH MULTI-USE INPUT CONTACTS AND RELATED METHODS
A semiconductor device includes a first contact receiving a first voltage, a second contact receiving a second voltage, one or more comparing elements...
2018/0166377 SEMICONDUCTOR DEVICE WITH STACKED TERMINALS
A semiconductor device includes housing, a substrate, a first semiconductor die, a second semiconductor die, a first terminal, and a second terminal. The first...
2018/0166376 SEMICONDUCTOR DEVICE
A semiconductor device (10) of the present invention includes at least one circuit unit (41, 42, 43) which includes: a device main body (20); and a power...
2018/0166375 Semiconductor Device, Electronic Component and Method
In an embodiment, a semiconductor device includes a galvanically isolated signal transfer coupler having a contact pad. The contact pad includes a metallic...
2018/0166374 WIRING SUBSTRATE
A wiring substrate includes a flexible insulation substrate, a first wiring layer formed on an upper surface of the insulation substrate, a second wiring layer...
2018/0166373 METHOD OF MAKING WIRING BOARD WITH INTERPOSER AND ELECTRONIC COMPONENT INCORPORATED WITH BASE BOARD
A wiring board includes an interposer and an electronic component laterally surrounded by a base board and a dielectric layer and connected to a routing...
2018/0166372 Wiring Substrate and Semiconductor Device
A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers...
2018/0166371 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure including a first redistribution circuitry and a second redistribution circuitry is provided. The first redistribution circuitry has a...
2018/0166370 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor substrate includes an interconnection structure and a dielectric layer. The dielectric layer surrounds the interconnection structure and...
2018/0166369 Bi-Layer Nanoparticle Adhesion Film
A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a...
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