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Patent # Description
2018/0166368 LEAD FRAME
A lead frame includes a metal plate, having a surface partitioned, by a concavity, into columnar areas, and a plating layer including stacked Ni, Pd and Au...
2018/0166367 FLIP-CHIP PACKAGING DIODE WITH A MULTICHIP STRUCTURE
A flip-chip packaging diode with a multichip structure includes at least two flip-chips arranged with an interval apart from each other and horizontally...
2018/0166366 SEMICONDUCTOR DEVICES INCLUDING EXPOSED OPPOSING DIE PADS
A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame...
2018/0166365 ELECTRONIC PACKAGE STRUCTURE
A method for providing an electronic package structure includes providing a substrate having a die pad having a die pad top surface and an opposing die pad...
2018/0166364 Package Structures and Method of Forming the Same
Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The...
2018/0166363 SEMICONDUCTOR PACKAGE WITH ELECTROMAGNETIC INTERFERENCE SHIELDING STRUCTURES
Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a...
2018/0166362 SEMICONDUCTOR STACKING STRUCTURE AND METHOD FOR MANUFACTURING THEREOF
A semiconductor stacking structure is provided. The semiconductor stacking structure includes a substrate and at least one conductor. The substrate has at...
2018/0166361 METHOD OF FORMING CONDUCTIVE BUMPS FOR COOLING DEVICE CONNECTION
A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface...
2018/0166360 MICROFLUIDIC ARRAY
An array (10) of flow units (100) for controlling a flow of a fluid is disclosed. The flow units (100) are arranged to have a lateral extension in a common...
2018/0166359 Electronics Assemblies and Cooling Structures Having Metalized Exterior Surface
An electronics assembly comprises a semiconductor device having a first device surface and at least one device conductive layer disposed on the first device...
2018/0166358 THERMALLY ENHANCED SEMICONDUCTOR PACKAGE AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the module...
2018/0166357 Heat Exchanger For Dual-Sided Cooling of Electronic Modules
A heat exchanger assembly has first and second heat sink elements enclosing fluid flow passages, and a clamping assembly. The heat sink elements are separated...
2018/0166356 FAN-OUT CIRCUIT PACKAGING WITH INTEGRATED LID
Various embodiments include integrated circuit (IC) package structures. In some cases, an IC package includes: a carrier having a recess; a plurality of IC...
2018/0166355 INTERPOSER MANUFACTURING METHOD
A plurality of interposers are made from a material substrate. The material substrate includes a glass substrate partitioned by a plurality of crossing...
2018/0166354 WIRING CIRCUIT SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD OF PRODUCING THE WIRING CIRCUIT SUBSTRATE, AND METHOD OF...
A wiring circuit substrate includes a glass base, insulating resin layers, wire groups, a first inorganic adhesive layer, a through electrode, and second...
2018/0166353 GLASS SUBSTRATE ASSEMBLIES HAVING LOW DIELECTRIC PROPERTIES
Glass substrate assemblies having low dielectric properties, electronic assemblies incorporating glass substrate assemblies, and methods of fabricating glass...
2018/0166352 SEMICONDUCTOR DEVICE HAVING A TRENCH TYPE DEVICE ISOLATION FILM AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a substrate having a semiconductor layer. A trench is formed within the semiconductor layer. A filling insulating film is...
2018/0166351 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
A semiconductor package includes a substrate, an integrated circuit die, a lid and an adhesive. The integrated circuit die is disposed over the substrate. The...
2018/0166350 Current Sensor And Method Of Making A Current Sensor
A current sensor comprises a current conductor having a first portion, a measuring portion and a second portion, the first portion including one or more first...
2018/0166349 FLUID DROPLET METHODOLOGY AND APPARATUS FOR IMPRINT LITHOGRAPHY
A method can be used to generate a fluid droplet pattern for an imprint lithography process using a fluid dispense system having fluid dispense ports. The...
2018/0166348 Scanning Methods For Focus Control For Lithographic Processing Of Reconstituted Wafers
A method of processing a reconstituted wafer that supports IC chips includes operably disposing the reconstituted wafer in a lithography tool that has a depth...
2018/0166347 SUBSTRATE FEATURES FOR INDUCTIVE MONITORING OF CONDUCTIVE TRENCH DEPTH
A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor...
2018/0166346 SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device manufacturing method includes setting a local target thickness of any one of a semiconductor wafer and a film formed on the...
2018/0166345 SEMICONDUCTOR DEVICES
A semiconductor device includes first and second select lines, first and second vertical pillars, and first and second subsidiary lines. The select lines are...
2018/0166344 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region...
2018/0166343 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each...
2018/0166342 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor device and a fabrication method are provided. The fabrication method includes providing a base substrate including a first region for forming a...
2018/0166341 INNOVATIVE APPROACH TO MINIMIZE PLASMA DOPING INDUCED FIN HEIGHT LOSS
A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height...
2018/0166340 METHOD AND APPARATUS OF MULTI THRESHOLD VOLTAGE CMOS
A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a...
2018/0166339 SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first ...
2018/0166338 BiMOS DEVICE WITH A FULLY SELF-ALIGNED EMITTER-SILICON AND METHOD FOR MANUFACTURING THE SAME
A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation...
2018/0166337 SYSTEMS AND METHODS FOR CONTROLLING RELEASE OF TRANSFERABLE SEMICONDUCTOR STRUCTURES
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
2018/0166336 SELF-ALIGNED CONTACT CAP
A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first...
2018/0166335 SELF-ALIGNED MIDDLE OF THE LINE (MOL) CONTACTS
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active...
2018/0166334 SEMICONDUCTOR DEVICE
A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact...
2018/0166333 SEMICONDUCTOR INTERCONNECT STRUCTURE HAVING A GRAPHENE BARRIER LAYER
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure...
2018/0166332 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first...
2018/0166331 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE USING POLISHING PROCESS
Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the...
2018/0166330 MULTI-METAL FILL WITH SELF-ALIGN PATTERNING
The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap...
2018/0166329 METHOD FOR FORMING SEMICONDUCTOR DEVICE CONTACT
A method of making a semiconductor device includes forming a gate stack that include a gate electrode and a spacer layer extending along a sidewall of the gate...
2018/0166328 SEMICONDUCTOR DIE HAVING EDGE WITH MULTIPLE GRADIENTS AND METHOD FOR FORMING THE SAME
A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor...
2018/0166327 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain...
2018/0166326 STRUCTURE AND METHOD FOR HIGH PERFORMANCE LARGE-GRAIN-POLY SILICON BACKPLANE FOR OLED APPLICATIONS
Large grain polysilicon films can be exfoliated on a handle substrate, such as a glass or glass-ceramic substrate. The large grain polysilicon can have high...
2018/0166325 GROUP III NITRIDE COMPOSITE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING GROUP...
Provided are a group III nitride composite substrate having a low sheet resistance and produced with a high yield, and a method for manufacturing the same, as...
2018/0166324 Buried Insulator Regions and Methods of Formation Thereof
A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and...
2018/0166323 SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
A method for fabricating an integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate is described herein....
2018/0166322 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating...
2018/0166321 SEMICONDUCTOR DEVICE WITH REDUCED TRENCH LOADING EFFECT
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having reduced trench...
2018/0166320 SEMICONDUCTOR DEVICES
A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the...
2018/0166319 AIR-GAP SPACERS FOR FIELD-EFFECT TRANSISTORS
Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on...
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