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Patent # Description
2018/0166166 USING IMAGE REFERENCES IN RADIOLOGY REPORTS TO SUPPORT REPORT-TO-IMAGE NAVIGATION
A system, method and computer readable storage medium for retrieving a narrative report for at least one study including a plurality of images of a patient...
2018/0166165 SYSTEM AND METHODS FOR DEVELOPING AND USING A MICROBIOME-BASED ACTION COMPONENT FOR PATIENT HEALTH
The invention relates generally to a system and methods by which a microbiome-based action component may be developed that is useful in order to establish,...
2018/0166164 METHODS AND SYSTEMS FOR MANAGING PATIENT TREATMENT COMPLIANCE
Provided are computer implemented method and systems for providing and monitoring patient compliance with a patient healthcare treatment plan. The method...
2018/0166163 SYSTEMS AND METHODS FOR MANAGING REGIMEN ADHERENCE
Systems and methods are provided for managing medical adherence. An exemplary method may include managing medical adherence utilizing data aggregating and...
2018/0166162 MEDICAL SYSTEM
The medical system of the embodiment comprises a recording unit, management unit, extracting unit, searching unit, and display unit. The recording unit records...
2018/0166161 A WORKFLOW MANAGEMENT SYSTEM AND RELATED METHOD FOR MULTI-AUTHOR REPORTING
A workflow management system for medical report production includes a workflow database that stores workflows, a user database that stores users, a task...
2018/0166160 SYSTEM AND METHOD FOR PROVIDING ACCESS TO ELECTRONICALLY STORED MEDICAL INFORMATION
A method and system for storing medical information of an individual with a service provider and providing access to that medical information to first...
2018/0166159 AGE-ADAPTIVE PULSE OXIMETRY
Embodiments are directed to age-adaptive physiologic monitoring. In one scenario, a method is provided for accessing an indication of a user's age. The method...
2018/0166157 Computational Systems and Methods for Health Services Planning and Matching
Systems and methods are described relating to detecting an indication of at least one attribute of an individual; accepting sensor data about the individual;...
2018/0166156 TEST DEVICE AND METHOD OF OPERATING THE SAME
The test device is configured of a device main body and a mobile terminal. The mobile terminal functions as an operation terminal of the device main body, and...
2018/0166155 SYSTEM AND METHOD FOR CORRELATING RETAIL TESTING PRODUCT TO MEDICAL DIAGNOSTIC CODE
A method for correlating a retail testing product to medical codes is provided. The method comprises receiving a diagnostic test identifier at a server...
2018/0166154 TEST PANEL TO MEASURE BLOOD NEUROTOXIN LEVELS IN PREMATERNAL WOMEN AND FOR THE GENERAL PUBLIC IN RELATION TO...
A prescribed diagnostic blood test panel is directed to countering autistic and mentally affected births and assessing the continued healthy mental state of...
2018/0166153 MEMORY AUTO REPAIRING CIRCUIT AND ASSOCIATED METHOD
a memory auto repairing circuit including: a decoding circuit, a latch enable circuit and a first latch circuit, wherein the decoding circuit is arranged to...
2018/0166152 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor device may include a repair address storage circuit, an address comparison circuit, and a word line selection circuit. The repair address...
2018/0166151 FERROELECTRIC MEMORY CELL RECOVERY
Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell...
2018/0166150 MEMORY DEVICE INCLUDING VIRTUAL FAIL GENERATOR AND MEMORY CELL REPAIR METHOD THEREOF
A memory device includes a memory cell array, a comparator, and a virtual fail generator. The memory cell array includes memory cells. The comparator...
2018/0166149 SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a...
2018/0166148 CONTROL METHOD FOR MEMORY DEVICE AND MEMORY CONTROLLER
A control method for a memory device is provided. The control method includes the following steps. Convert multiple input bits on multiple bit-channels into a...
2018/0166147 SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD THEREOF
A semiconductor device preventing reduction of reliability due to the impact of heat after shipment is provided. A semiconductor device of the disclosure...
2018/0166146 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation...
2018/0166145 RETENTION MINIMUM VOLTAGE DETERMINATION TECHNIQUES
An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage...
2018/0166144 SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND OPERATING METHOD THEREOF
A semiconductor device includes an internal command generation circuit suitable for generating a first internal command, a second internal command, and a third...
2018/0166143 Memory Device with a Fuse Protection Circuit
A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes...
2018/0166142 FLASH COMMAND THAT REPORTS A COUNT OF CELL PROGRAM FAILURES
An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies....
2018/0166141 NON-VOLATILE MEMORY ARRAY WITH MEMORY GATE LINE AND SOURCE LINE SCRAMBLING
A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the...
2018/0166140 MEMORY ARCHITECTURE HAVING TWO INDEPENDENTLY CONTROLLED VOLTAGE PUMPS
A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first...
2018/0166139 METHOD AND APPARATUS FOR PROVIDING MULTI-PAGE READ AND WRITE USING SRAM AND NONVOLATILE MEMORY DEVICES
A memory device includes a static random-access memory ("SRAM") circuit and a first nonvolatile memory ("NVM") string, a second NVM string, a first and a...
2018/0166138 RESISTANCE VARIABLE ELEMENT METHODS AND APPARATUSES
Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a...
2018/0166137 PROGRAMMING FOR ELECTRONIC MEMORIES
Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively...
2018/0166136 MEMORY DEVICE AND METHOD FOR OPERATING MEMORY DEVICE
A memory device and a method for operating the memory device are provided. A resistive memory cell connected to a first node and configured to include a...
2018/0166135 Resistive Random Access Memory Cell
A resistive random access memory cell includes three resistive random access memory devices, each resistive random access memory device having an ion source...
2018/0166134 COMPENSATED READOUT OF A MEMRISTOR ARRAY, A MEMRISTOR ARRAY READOUT CIRCUIT, AND METHOD OF FABRICATION THEREOF
A method for readout of a gated memristor array, a memristor array readout circuit and method of fabrication thereof are provided. In the context of the...
2018/0166133 REFERENCE CURRENTS FOR INPUT CURRENT COMPARISONS
An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is to...
2018/0166132 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is...
2018/0166131 MEMORY WITH SYMMETRIC READ CURRENT PROFILE AND READ METHOD THEREOF
Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array...
2018/0166130 CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a...
2018/0166129 WRITE DRIVER SCHEME FOR BIT-WRITABLE MEMORIES
The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a...
2018/0166128 CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT SRAM
A memory array has word lines and bit lines. A row decoder is operable to decode a row address and select a corresponding word line. A read-write clock...
2018/0166127 READ ASSIST CIRCUIT WITH PROCESS, VOLTAGE AND TEMPERATURE TRACKING FOR A STATIC RANDOM ACCESS MEMORY (SRAM)
A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit. The memory circuit further includes a read assist...
2018/0166126 WRITE ASSIST FOR MEMORIES WITH RESISTIVE BIT LINES
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with...
2018/0166125 Memory Cell of Static Random Access Memory Based on Resistance and Capacitance Hardening
The present invention provides a memory cell of static random access memory based on resistance-capacitance reinforcement, which comprises a latch circuit and...
2018/0166124 SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE
A semiconductor device in which a plurality of chips each including a memory circuit is stacked, the semiconductor device includes a transmission path...
2018/0166123 SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device in which a plurality of chips each including a memory circuit are stacked, the semiconductor device includes measurement circuitry each...
2018/0166122 MULTI CHANNEL SEMICONDUCTOR DEVICE HAVING MULTI DIES AND OPERATION METHOD THEREOF
A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to...
2018/0166121 MULTI-DIE MEMORY DEVICE
A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and...
2018/0166120 FLOATING BODY DRAM WITH REDUCED ACCESS ENERGY
Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells...
2018/0166119 SUB WORD LINE DRIVER OF SEMICONDUCTOR MEMORY DEVICE
A layout structure of a sub word line driver for use in a semiconductor memory device may be disclosed. The sub word line driver may include a first active...
2018/0166118 MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION
A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at...
2018/0166117 MEMROY DEVICE AND OPERATING METHOD THEREOF
An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality...
2018/0166116 DIMM DRAM MEMORY CHIPS QUICK OPTICAL DATA ERASURE AFTER POWER CYCLING
Quick optical DRAM reset and data erasure can be performed during power down (power cycling) or chip cooling and removal from the socket. In this way cold boot...
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