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Patent # Description
2018/0165254 METHOD AND SYSTEM FOR VISUALIZING OR INTERACTING WITH ARRAY DATA USING LIMITED-RESOLUTION DISPLAY DEVICES
Methods and computer systems are disclosed for displaying and interacting with array data on a display device. Limited display device resolutions can...
2018/0165253 INFORMATION ARCHITECTURE FOR THE INTERACTIVE ENVIRONMENT
A system and method for providing management such as creation, manipulation, storage, control, and retrieval of digital content for a company on a global...
2018/0165252 METHOD FOR ESTIMATING SUITABILITY AS MULTI-SCREEN PROJECTING TYPE THEATRE SYSTEM
The present disclosure relates to a method and a device for estimating suitability as a multi-screen projecting type theatre and the method for estimating the...
2018/0165251 METHOD AND AN APPARATUS FOR ENCODING A SIGNAL TRANSPORTING DATA FOR RECONSTRUCTING A SPARSE MATRIX
The disclosure relates to method for storing and transmitting sparse matrices in compact way. When storing and manipulating sparse matrices on a device, it is...
2018/0165250 Data Processing Method and Processor based on 3072-Point Fast Fourier Transformation, and Storage Medium
A method for processing data based on 3072-point Fast Fourier Transform (FFT) and a processor based on 3072-point FFT are provided. The method for processing...
2018/0165249 FRACTIONAL SCALING DIGITAL FILTERS AND THE GENERATION OF STANDARDIZED NOISE AND SYNTHETIC DATA SERIES
A method for processing a digital signal comprises identifying a desired frequency and/or phase response that is represented in a frequency domain ...
2018/0165248 SYSTEMS AND METHODS FOR PERFORMING LINEAR ALGEBRA OPERATIONS USING MULTI-MODE OPTICS
Under one aspect, a method for performing a linear algebra operation includes imposing matrix elements onto a chirped optical carrier; inputting into a...
2018/0165247 OFF-BOARD HOURS-OF-SERVICE ("HOS") PROCESSING
Systems, methods, and devices for providing hour-of-service ("HOS") calculations via a web based host server instead of on an onboard mobile device. In the...
2018/0165246 MULTI-CORE PROCESSOR AND OPERATION METHOD THEREOF
A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform...
2018/0165245 PARALLEL PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM
A parallel processing apparatus including a plurality of compute nodes and a management node including a first processor configured to execute a process...
2018/0165244 CONFIGURABLE PCIe BANDWIDTH UTILIZATION BETWEEN PCI RISER AND OTHER INTERNAL FUNCTIONS
Embodiments allow an IHS to be configured for different distributions of available PCIe bandwidth. An IHS is reconfigured by utilizing different PCIe riser...
2018/0165243 SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of memory chips arranged in a line on a substrate, and a bus connected to the plurality of memory chips and...
2018/0165242 METHOD AND APPARATUS FOR GROUPING MULTIPLE SAS EXPANDERS TO FORM A SINGLE COHESIVE SAS EXPANDER
A SAS (Serial Attached SCSI or Serial Attached Small Computer System Interface) switch includes a master SAS expander and a multitude of slave expanders...
2018/0165241 CHANNEL SWITCHING DEVICE, MEMORY STORAGE DEVICE AND CHANNEL SWITCHING METHOD
A channel switching device, a memory storage device and a channel switching method are provided. The channel switching device includes a signal analysis module...
2018/0165240 INTERCONNECT NETWORK SUPPORTING MULTIPLE CONSISTENCY MECHANISMS, MULTIPLE PROTOCOLS, AND MULTIPLE SWITCHING...
A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second...
2018/0165239 OPTIMIZING ROUTING OF A SIGNAL PATH IN A SEMICONDUCTOR DEVICE
Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at...
2018/0165238 SELF-TUNE CONTROLLER
Example implementations relate to a self-tune controller. For example, the self-tune controller may poll, via an out-of-band data stream, low-level operation...
2018/0165237 SERVER SYSTEM
The present disclosure provides a server system including a rack, a rack management controller, host devices, storage devices and two signal switches. The rack...
2018/0165236 DEVICE AND METHOD FOR ADDRESSING, AND CONVERTER
It is provided to implement a different number of logical slaves in a field device for use in an AS interface network as a function of the assigned address,...
2018/0165235 DISPLAY DEVICE AND METHOD OF DRIVING THE SAME
A display device includes a first connector which receives a first image signal and first driving power, a second connector which receives a second image...
2018/0165234 MULTI MEDIA DATA STORING AND TRANSMITTING APPARATUS
An multi media data storing and transmitting apparatus includes a control module engaged in a receptacle, the control module includes a voltage output...
2018/0165233 NETWORK CONTROLLER - SIDEBAND INTERFACE PORT CONTROLLER
A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an...
2018/0165232 SLAVE DEVICE CONNECTED TO MASTER DEVICE VIA I2C BUS AND COMMUNICATION METHOD THEREOF
The present disclosure discloses a communication method for a slave device connected to a master device via an I2C bus. The method includes detecting the...
2018/0165231 MICROCOMPUTER
A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication...
2018/0165230 ELECTRONIC CONTROL UNIT AND DATA TRANSMISSION METHOD
An electronic control unit connected to a communication line, the electronic control unit including: a transmission request buffer including a plurality of...
2018/0165229 URGENCY BASED REORDERING FOR PRIORITY ORDER SERVICING OF MEMORY REQUESTS
Embodiments of the invention include a machine-readable medium having stored thereon instructions, which if performed by a machine causes the machine to...
2018/0165228 Fabric Independent PCIE Cluster Manager
A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster...
2018/0165227 Portable Entertainment System
A portable entertainment system has a base unit and a remote computing device. The base unit has an electronics apparatus, the electronics apparatus has a base...
2018/0165226 MEMORY PRIVILEGE
A method for executing a process on a device, the device comprising one or more processors for executing the process and a memory, wherein the process has an...
2018/0165225 EFFICIENTLY STORING INTIALIZATION VECTORS
Examples relate to efficient storage of initialization vectors in a system. One example facilitates determining an initialization vector for use in encrypting...
2018/0165224 SECURE ENCRYPTED VIRTUALIZATION
Systems, apparatuses, and methods for implemented secure encrypted virtualization are disclosed. In one embodiment, a system includes at least one or more main...
2018/0165223 METHODS OF OPERATING MEMORY SYSTEM
A method of operating a memory system includes setting a secured area in a volatile memory device of the memory system during a secure mode, writing secure...
2018/0165222 INVALIDATING READS FOR CACHE UTILIZATION IN PROCESSORS
In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct...
2018/0165221 NO ALLOCATE CACHE POLICY
A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an...
2018/0165220 EXPIRING VIRTUAL CONTENT FROM A CACHE IN A VIRTUAL UNIVERSE
Approaches for expiring cached virtual content in a virtual universe are provided. In one approach, there is an expiration tool, including an identification...
2018/0165219 MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME
A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the...
2018/0165218 MEMORY MANAGEMENT
Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address...
2018/0165217 MULTI-LEVEL CACHE WITH ASSOCIATIVITY COLLISION COMPENSATION
In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines...
2018/0165216 METHODS AND SYSTEMS FOR DIRECTLY MAPPING A BACKEND BLOCK ADDRESS INTO A PHYSICAL ADDRESS OF A CACHING DEVICE
A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The...
2018/0165215 METHODS AND SYSTEMS FOR INVALIDATING MEMORY RANGES IN FABRIC-BASED ARCHITECTURES
Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the...
2018/0165214 DYNAMIC CACHE BYPASSING
A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when...
2018/0165213 METHOD AND APPARATUS FOR MEMORY CONSISTENCY USING CACHE COHERENCY PROTOCOLS
A request is received from a first node over a communication fabric, the request to acquire an access right of a cache line for accessing data stored in a...
2018/0165212 HIGH-PERFORMANCE INSTRUCTION CACHE SYSTEM AND METHOD
A high-performance instruction cache method based on extracting instruction information and store in a track table. The method enables reading of all levels of...
2018/0165211 SYSTEM AND METHOD FOR STORE STREAMING DETECTION AND HANDLING
According to one general aspect, an apparatus may include a load/store circuit and a region size detection circuit. The load/store circuit may be configured to...
2018/0165210 SYSTEM, APPARATUS AND METHOD FOR DYNAMIC PROFILING IN A PROCESSOR
In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a...
2018/0165209 MEMORY ALLOCATION SYSTEM FOR MULTI-TIER MEMORY
A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The...
2018/0165208 SYSTEMS AND METHODS FOR CACHING DATA
The various embodiments described herein include methods, devices, and systems for caching data. In one aspect, a method is performed at a computing system...
2018/0165207 SYSTEM AND METHOD TO INCREASE AVAILABILITY IN A MULTI-LEVEL MEMORY CONFIGURATION
One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second...
2018/0165206 METHODS, SYSTEMS AND APPARATUS FOR PREDICTING THE WAY OF A SET ASSOCIATIVE CACHE
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of...
2018/0165205 OPPORTUNISTIC INCREASE OF WAYS IN MEMORY-SIDE CACHE
A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of...
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