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Patent # Description
2018/0175906 CYCLIC-FREQUENCY SHIFT ORTHOGONAL FREQUENCY DIVISION MULTIPLEX DEVICE
The invention discloses a cyclic-Frequency shift orthogonal frequency division multiplex spread spectrum device, comprising: at least one communication device...
2018/0175905 SYSTEMS AND METHODS FOR SPECTRALLY EFFICIENT AND ENERGY EFFICIENT ULTRA-WIDEBAND IMPULSE RADIOS AND SCALABLE...
Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data...
2018/0175904 METHOD AND APPARATUS FOR RANDOMIZATION OF INTERFERENCE IN CELLULAR INTERNET OF THINGS (IOT) SYSTEM
A method and apparatus for randomization of interference in a cellular Internet of things (IoT) system is disclosed. The method for randomization of...
2018/0175903 SPREAD SPECTRUM ACOUSTIC COMMUNICATION TECHNIQUES
In a transmit method, a set of data eigenvectors that are based on a Prometheus Orthonormal Set (PONS) code construction and orthogonal to each other are...
2018/0175902 DUPLEXER WITH SIGNAL CANCELLATION
A wireless communication system has a base station operative to communicate wirelessly with a plurality of customer devices. The base station has a circulator...
2018/0175901 MULTILAYER PRINTED CIRCUIT BOARD AND ELECTRONIC DEVICE INCLUDING THE SAME
A multilayer printed circuit board (PCB) including a plurality of substrate layers formed in stack is provided. The multilayer printed circuit board includes a...
2018/0175900 AUXILIARY CHANNEL TRANSCEIVING CIRCUIT OF DISPLAYPORT INTERFACE
An auxiliary channel transceiving circuit includes: a first node and a second node; a first voltage-dividing circuit for generating a first received signal...
2018/0175899 Assessment And/Or Design of Multiple-Antenna Systems
In a method for determining the performance of at least one antenna in a system including a plurality of antennas, the method subdivides a reception area...
2018/0175898 RF TRANSCEIVER WITH TEST CAPABILITY
An RF front-end circuit of an RF transceiver is described herein. In accordance with one exemplary embodiment, the fronted circuit includes a local oscillator...
2018/0175897 Radio Remote Unit, Receiver, And Base Station
Embodiments of the present disclosure disclose a radio remote unit, a receiver, and a base station. The radio remote unit includes at least one receive channel...
2018/0175896 RECEIVERS AND METHODS FOR REDUCING AN INTERFERENCE COMPONENT IN A RECEIVE SIGNAL
A receiver for reducing an interference component in a receive signal is provided. The interference component is caused by a first interferer emitting payload...
2018/0175895 FILTER DESIGN FOR ACCESS POINTS
Receiving filter design that reduces out-of-channel interference for APs is disclosed. An AP includes a first radio and a second radio disposed in a body of...
2018/0175894 COMMUNICATION DEVICE AND COMMUNICATION METHOD
There is provided a communication device configured to limit a frequency band of a transmission signal including a plurality of signals to be wirelessly...
2018/0175893 SYSTEMS AND METHODS FOR A PREDISTORTION LINEARIZER WITH FREQUENCY COMPENSATION
An analog predistortion linearizer system with dynamic frequency compensation for automatically adjusting predistortion characteristics based on a detected...
2018/0175892 METHOD AND APPARATUS FOR COUPLING AN ANTENNA TO A DEVICE
Aspects of the subject disclosure may include, for example, receiving, by a feed point of a dielectric antenna, electromagnetic waves from a dielectric core...
2018/0175891 TRANSMITTER FOR WIRELESS COMMUNICATIONS
A transmitter for wireless communications can remove a signal having an image frequency without using a band pass filter, and can be downsized such that it is...
2018/0175890 Methods and Apparatus for Error Correction Coding Based on Data Compression
Embodiments are generally related to the field of channel and source coding of data to be sent over a channel, such as a communication link or a data memory....
2018/0175889 ADAPTIVE BIT-FLIPPING DECODER BASED ON DYNAMIC ERROR INFORMATION
A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select...
2018/0175888 EFFICIENT ENCODING/DECODING FOR MULTIPLE-INPUT MULTIPLE-OUTPUT OPERATING WITH TWO CODEWORDS
Various communication systems may benefit from efficient encoding and decoding. For example, certain multiple-input multiple-output devices may benefit from...
2018/0175887 HIGH PERFORMANCE DATA REDUNDANCY AND FAULT TOLERANCE
One embodiment provides a system that facilitates numerical operation-based erasure coding. During operation, the system determines the bit-width of processing...
2018/0175886 APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation...
2018/0175885 Hybrid LDPC-SEC/SECDED Decoding
A solid state storage device, comprising a non-volatile memory configured to store data encoded into a plurality of encoded data groups, each encoded data...
2018/0175884 METHOD FOR RECEIVING A BROADCAST SIGNAL AND BROADCAST RECEIVER DEVICE
The present disclosure relates to a method and system for receiving a broadcast signal. The system includes a broadcast receiver device having two receiving...
2018/0175883 PARALLEL PIPELINE LOGIC CIRCUIT FOR GENERATING CRC VALUES UTILIZING LOOKUP TABLE
CRC generation circuitry includes a lookup-table storing N-bit CRC values for M one-hot data frames. N AND gates for each bit of a M-bit data frame receive...
2018/0175882 LOW POWER ERROR CORRECTING CODE (ECC) SYSTEM
A system for an Error Correction Code ("ECC") decoder includes a first decoder and a second decoder. The first decoder is configured to determine a first...
2018/0175881 OPTIMIZED CODE TABLE SIGNALING FOR AUTHENTICATION TO A NETWORK AND INFORMATION SYSTEM
In various embodiments, a system comprising a network interface, a processor, and a non-transient memory medium operatively coupled to the processor is...
2018/0175880 MEMORY COMPRESSION OPERABLE FOR NON-CONTIGUOUS WRITE/READ ADDRESSES
Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first...
2018/0175879 POWER-SAVING CURRENT-MODE DIGITAL-TO-ANALOG CONVERTER (DAC)
A digital-to-analog converter (DAC) for an audio system in a media device, such as a portable media device or smart phone, may be operated to turn off portions...
2018/0175878 APPARATUS FOR INTERPOLATING BETWEEN A FIRST SIGNAL EDGE AND A SECOND SIGNAL EDGE, A METHOD FOR CONTROLLING SUCH...
An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells...
2018/0175877 DIGITAL TO ANALOG CONVERSION CIRCUIT AND DATA SOURCE CIRCUIT CHIP
The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the...
2018/0175876 ANALOG-TO-DIGITAL CONVERTERS
An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current...
2018/0175875 ANALOG-TO-DIGITAL CONVERTER
The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a...
2018/0175874 METHOD OF GAIN CALIBRATION IN A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND A SUCCESSIVE...
A method of gain calibration in a SAR ADC is disclosed. In one aspect, the method comprises determining a number of bits of an analog input signal (V.sub.IN),...
2018/0175873 BAND SPECIFIC INTERLEAVING MISMATCH COMPENSATION IN RF ADCS
An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a...
2018/0175872 ATOMIC OSCILLATOR AND A METHOD OF GENERATING ATOMIC OSCILLATION
An atomic oscillator includes: an atomic cell containing metal atoms; a light source generating light to be emitted to the atomic cell; a driver outputting a...
2018/0175871 HIGH FREQUENCY SYNTHESIS AND DUTY CYCLE CONTROL WITH INTERPOLATIVE DIVIDERS USING A LOW SPEED INTERFACE
An interpolative divider includes a look ahead sigma delta modulator circuit to generate divide values according to a divide ratio. A plurality of M storage...
2018/0175870 EXTENDED PERIOD TIMER CIRCUITS FOR OPHTHALMIC DEVICES
Programmable timer circuits are disclosed. One timer circuit may include a reference circuit configured to generate a bias current, a current controlled...
2018/0175869 Stacked Synthesizer For Wide Local Oscillator Generation Using A Dynamic Divider
A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled...
2018/0175868 GENERATION OF FAST FREQUENCY RAMPS
A circuit includes an RF oscillator coupled in a phase-locked loop. The phase-locked loop is configured to receive a digital input signal, which is a sequence...
2018/0175867 SYSTEMS AND METHODS FOR CORRECTING DETERMINISTIC JITTER IN AN ALL-DIGITAL PHASE LOCKED LOOP
A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input...
2018/0175866 SEMICONDUCTOR DEVICE AND CONTROL SYSTEM
An abnormal rise of oscillation frequencies of PLL circuits in conventional semiconductor devices has been an inevitable problem. This semiconductor device...
2018/0175865 WIDE CAPTURE RANGE REFERENCE-LESS FREQUENCY DETECTOR
A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control...
2018/0175864 MONOTONIC COUNTER AND METHOD OF OPERATING A MONOTONIC COUNTER
The present application relates to a system hosting a monotonic counter and a method of operating the system. The system comprises a non-volatile memory (110)...
2018/0175863 WAVE-BASED MAJORITY GATE DEVICE
The disclosed technology generally relates to computation devices, and more particularly to majority gate devices configured for computation based on spin...
2018/0175862 PROGRAMMABLE LOGIC DESIGN
A programmable logic unit (PLU). The PLU includes a plurality of four-input reconfigurable hard logics (RHLs), a three-input look-up-table (LUT), and a...
2018/0175861 INFORMATION PROCESSING DEVICE, PLD MANAGEMENT PROGRAM, AND PLD MANAGEMENT METHOD
An information processing device includes a processor configured to execute a program; and a programmable circuit device (a PLD hereafter) having a...
2018/0175860 TRANSMITTER CIRCUIT AND RECEIVER CIRCUIT FOR OPERATING UNDER LOW VOLTAGE
A transmitter circuit including a pre-driver circuit configured to receive a logic signal from a logic circuit and to generate a first signal driven by a first...
2018/0175859 HIGH VOLTAGE TOLERANT CMOS DRIVER FOR LOW-VOLTAGE BI-DIRECTIONAL COMMUNICATION BUSES
This application relates to a bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state....
2018/0175858 ADAPTIVE POWER SAVING IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) IN OPTICAL MODULE
An apparatus for saving power in an field programmable gate array (FPGA) in an optical communication device is provided. The apparatus includes at least one...
2018/0175857 PANE ARRANGEMENT WITH PANE WITH LOW-E COATING AND CAPACITIVE SWITCHING REGION
A pane arrangement having a pane with an inner surface and an outer surface, a low-E coating arranged on the inner surface of the pane. The pane arrangement...
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