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Patent # Description
2018/0175201 FinFET Structures and Methods of Forming the Same
A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate...
2018/0175200 PMOS FinFET
A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process...
2018/0175199 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A substrate includes a pattern forming region and a peripheral region. A first strain relaxed buffer layer is disposed on the pattern forming region of the...
2018/0175198 DEVICE WITH DIFFUSION BLOCKING LAYER IN SOURCE/DRAIN REGION
One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in...
2018/0175197 SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to...
2018/0175196 Semiconductor Epitaxy Bordering Isolation Structure
A method includes providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region...
2018/0175195 HIGH PRESSURE LOW THERMAL BUDGE HIGH-K POST ANNEALING PROCESS
A method of embedding SiGe when fabricating a PMOS device is provided. Multiple layers of SiGe layers with different Ge contents may be formed such that the Ge...
2018/0175194 METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH A COMPRESSIVE STRESSED CHANNEL
A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a...
2018/0175193 Double-Gate Vertical Transistor Semiconductor Device
A semiconductor device is disclosed that includes a substrate and at least a first, second, third, and fourth vertical transistor supported by the substrate....
2018/0175192 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A recessed portion is formed in a top surface of an isolation insulation film filling an isolation trench between a p.sup.+ source region and a p.sup.+ drain...
2018/0175191 LDMOS Transistor with Segmented Gate Dielectric Layer
A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of...
2018/0175190 VERTICAL DOUBLE DIFFUSION METAL-OXIDE-SEMICONDUCTOR POWER DEVICE WITH HIGH VOLTAGE START-UP UNIT
A vertical double diffusion metal-oxide-semiconductor power device with high voltage start-up unit includes a vertical double diffusion ...
2018/0175189 SEMICONDUCTOR DEVICE INCLUDING AUXILIARY STRUCTURE
One or more embodiments disclose a semiconductor device that includes a trench extending into a drift zone of a semiconductor body from a surface of the...
2018/0175188 HIGH VOLTAGE MOSFET DEVICES AND METHODS OF MAKING THE DEVICES
A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+...
2018/0175187 Semiconductor Device Comprising a Plurality of Transistor Cells and Manufacturing Method
A semiconductor device comprises a plurality of transistor cells. Each one of the plurality of transistor cells comprises a trench extending into a drift zone...
2018/0175186 SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE
A semiconductor substrate and a semiconductor device are disclosed. The semiconductor substrate includes a base layer, a buffer layer disposed on the base...
2018/0175185 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a...
2018/0175184 GALLIUM NITRIDE (GaN) TRANSISTOR STRUCTURES ON A SUBSTRATE
Techniques are disclosed for gallium nitride (GaN) oxide isolation and formation of GaN transistor structures on a substrate. In some cases, the GaN transistor...
2018/0175183 Semiconductor Component with Protrusion Propagation Body and Corresponding Methods of Manufacture
A semiconductor structure includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a...
2018/0175182 HETERO-JUNCTION BIPOLAR TRANSISTOR AND ELECTRIC DEVICE
This hetero-junction bipolar transistor includes a first n-type GaN layer, an Al.sub.xGa.sub.1-xN layer (0.1.ltoreq.x.ltoreq.0.5), an undoped GaN layer having...
2018/0175181 BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME
A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are...
2018/0175180 BIPOLAR JUNCTION TRANSISTORS WITH A COMBINED VERTICAL-LATERAL ARCHITECTURE
Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical...
2018/0175179 SYMMETRICAL LATERAL BIPOLAR JUNCTION TRANSISTOR AND USE OF SAME IN CHARACTERIZING AND PROTECTING TRANSISTORS
A symmetrical lateral bipolar junction transistor (SLBJT) is provided. The SLBJT includes a p-type semiconductor substrate, a n-type well, an emitter of a...
2018/0175178 METHOD OF MANUFACTURING OXIDE THIN FILM TRANSISTOR
There is provided a method of manufacturing an oxide thin film transistor (TFT). The method includes forming a gate electrode on a substrate, forming a gate...
2018/0175177 METHOD OF MANUFACTURING THIN FILM TRANSISTOR
The present application discloses a method of manufacturing a thin film transistor, including following steps: forming a gate electrode on the top surface of...
2018/0175176 CASCODED HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR
A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the...
2018/0175175 Conformal Transfer Doping Method For Fin-Like Field Effect Transistor
Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped...
2018/0175174 SHALLOW, ABRUPT AND HIGHLY ACTIVATED TIN EXTENSION IMPLANT JUNCTION
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shallow, abrupt and highly activated tin (Sn)...
2018/0175173 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin...
2018/0175172 FinFET Structures and Methods of Forming the Same
A method includes forming a first fin and a second fin over a substrate, depositing an isolation material surrounding the first and second fins, forming a gate...
2018/0175170 Source and Drain Formation Technique for Fin-Like Field Effect Transistor
Source and drain formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin...
2018/0175169 INTEGRATION PROCESS OF FINFET SPACER FORMATION
A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel...
2018/0175168 Vertical Power MOSFET and Methods for Forming the Same
A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate...
2018/0175167 METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INNER SPACERS
A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active...
2018/0175166 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED INTERNAL SPACERS
Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and...
2018/0175165 Etching Back and Selective Deposition of Metal Gate
A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate...
2018/0175164 3D Capacitor and Method of Manufacturing Same
A three-dimensional (3D) capacitor includes a semiconductor substrate; a fin structure including one or more fins formed on the semiconductor substrate; an...
2018/0175163 METHOD FOR MAKING A SEMICONDUCTOR DEVICE WITH NANOWIRE AND ALIGNED EXTERNAL AND INTERNAL SPACERS
Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer...
2018/0175162 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE WITH MULTI SPACERS
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a...
2018/0175161 METHOD FOR PROVIDING A LOW-k SPACER
A method for forming semiconductor devices with spacers is provided. SiCO spacers are formed on sides of features. Protective coverings are formed over first...
2018/0175160 PREPARATION METHOD FOR PLATFORM-SHAPED ACTIVE REGION BASED P-I-N DIODE STRING IN RECONFIGURABLE LOOP ANTENNA
A preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna includes: (a) selecting an SOI substrate;...
2018/0175159 Bi-Layer Metal Deposition in Silicide Formation
A method includes performing a first sputtering to form a first metal film on a surface of a semiconductor region. The first sputtering is performed using a...
2018/0175158 Transient Devices Designed to Undergo Programmable Transformations
The invention provides transient devices, including active and passive devices that electrically and/or physically transform upon application of at least one...
2018/0175157 METHOD FOR AVOIDING IL REGROWN IN A HKMG PROCESS
The present disclosure addresses and solves the current problem of oxygen accumulation in IL after an HKMG stack is formed. A fabrication method is provided...
2018/0175156 BINARY METAL OXIDE BASED INTERLAYER FOR HIGH MOBILITY CHANNELS
A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate...
2018/0175155 GATE STRUCTURE WITH DUAL WIDTH ELECTRODE LAYER
A high-k dielectric metal gate (HKMG) transistor includes a substrate, an HKMG gate stack with a gate dielectric layer and a gate electrode layer positioned...
2018/0175154 SEMICONDUCTOR DEVICE FOR COMPENSATING INTERNAL DELAY, METHODS THEREOF, AND DATA PROCESSING SYSTEM HAVING THE SAME.
A method of manufacturing a field effect transistor using a gate last process includes providing the field effect transistor which includes a high-k dielectric...
2018/0175153 SEMICONDUCTOR DEVICES AND METHODS FOR FORMING SEMICONDUCTOR DEVICES
A semiconductor device includes a transistor doping region of a vertical transistor structure arranged in a semiconductor substrate. Additionally, the...
2018/0175152 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of...
2018/0175151 FIN-TYPE SEMICONDUCTOR DEVICE
Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality...
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