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Patent # Description
2018/0175050 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer...
2018/0175049 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: forming an insulating film above a semiconductor substrate; forming a conductive film on the...
2018/0175048 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
A nonvolatile semiconductor storage device having a control gate formed on a semiconductor substrate and including a cylindrical through hole. A block...
2018/0175047 SEMICONDUCTOR DEVICE
A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor...
2018/0175046 Source and Drain Formation Technique for Fin-Like Field Effect Transistor
Source and drain formation techniques are disclosed herein for fin-like field effect transistors (FinFETs). An exemplary method for forming epitaxial...
2018/0175045 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating...
2018/0175044 MEMORY DEVICE WITH MANUFACTURABLE CYLINDRICAL STORAGE NODE
A high capacitance embedded capacitor and associated fabrication processes are disclosed for fabricating a capacitor stack in a multi-layer stack to include a...
2018/0175043 MICRO-PATTERN FORMING METHOD, CAPACITOR AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE AND METHOD...
A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting...
2018/0175042 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes: forming a transistor in a semiconductor substrate; forming a capacitor including a ...
2018/0175041 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in...
2018/0175040 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device is provided. The provided semiconductor device may have enhanced reliability and operating characteristics. The semiconductor device...
2018/0175039 Conductive Structures, Wordlines and Transistors
Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive...
2018/0175038 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
A method for fabricating a semiconductor device includes forming a device isolation film on a substrate between first and second regions, forming first and...
2018/0175037 METHOD, APPARATUS, AND SYSTEM HAVING SUPER STEEP RETROGRADE WELL WITH SILICON AND SILICON GERMANIUM FINS
At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an...
2018/0175036 Multi-Gate Device and Method of Fabrication Thereof
A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first...
2018/0175035 SEMICONDUCTOR DEVICES AND METHOD OF MANUFACUTRING THE SAME
A semiconductor device includes a first transistor in a first region and a second transistor in a second region. The first transistor includes: a first...
2018/0175034 LOGIC CIRCUIT BLOCK LAYOUTS WITH DUAL-SIDE PROCESSING
An integrated circuit device may include a p-type metal oxide semiconductor (PMOS) transistor supported by a backside of an isolation layer. The integrated...
2018/0175033 MEMORY WITH SINGLE-EVENT LATCHUP PREVENTION CIRCUITRY
An integrated circuit that includes an array of random-access memory cells is provided. Each memory cell may include inverting circuits formed from pull-up...
2018/0175032 Fin-Like Field Effect Transistor (FinFET) Device and Method of Manufacturing Same
A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material...
2018/0175031 INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF
An integrated circuit includes first and second semiconductor fins, first and second epitaxy structures, and first and second dielectric fin sidewall...
2018/0175030 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a core device disposed above the substrate, and an input/output (I/O) device disposed above the substrate. The...
2018/0175029 Integrated Circuit With A Gate Structure And Method Making The Same
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second...
2018/0175028 PREPARATION METHOD FOR HETEROGENEOUS SiGe BASED PLASMA P-I-N DIODE STRING FOR SLEEVE ANTENNA
A preparation method for a SiGe based plasma p-i-n diode string for a sleeve antenna is provided. The preparation method includes: selecting a SiGeOI substrate...
2018/0175027 MANUFACTURING METHOD FOR AlAs-Ge-AlAs STRUCTURE BASED PLASMA P-I-N DIODE IN MULTILAYERED HOLOGRAPHIC ANTENNA
A manufacturing method for an AlAs--Ge--AlAs structure based plasma p-i-n diode in a multilayered holographic antenna is provided. The manufacturing method...
2018/0175026 ROM Chip Manufacturing Structures
An integrated circuit (IC) chip embodiment includes first and second ROM cells arranged in a same row of a ROM array. The first and second ROM cells include...
2018/0175025 VERTICAL TRANSISTORS AND METHODS OF FORMING SAME
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region...
2018/0175024 INTEGRATED CIRCUIT HAVING VERTICAL TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE INTEGRATED CIRCUIT
An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in...
2018/0175023 DUMMY CONTACTS TO MITIGATE PLASMA CHARGING DAMAGE TO GATE DIELECTRICS
A method of limiting plasma charging damage on ICs. A die includes gate stacks on active areas defined by a field dielectric. A pre-metal dielectric (PMD)...
2018/0175022 METHOD OF FORMING MOS AND BIPOLAR TRANSISTORS
Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar...
2018/0175021 ISOLATION STRUCTURE FOR IC WITH EPI REGIONS SHARING THE SAME TANK
An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric...
2018/0175020 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
Semiconductor devices including a diode and a resistor are disclosed herein. An example of a semiconductor device includes a substrate having a surface. A...
2018/0175019 VERTICAL DOUBLE DIFFUSION METAL-OXIDE-SEMICONDUCTOR POWER DEVICE
A vertical double diffusion metal-oxide-semiconductor power device with thermal sensitivity unit includes a vertical double diffusion metal-oxide-semiconductor...
2018/0175018 TRANSIENT-VOLTAGE-SUPPRESSION (TVS) DIODE DEVICE AND METHOD OF FABRICATING THE SAME
A transient-voltage-suppression (TVS) diode device and a method of fabricating the same are disclosed. The TVS diode device includes a substrate. A second...
2018/0175017 APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are...
2018/0175016 SEMICONDUCTOR DEVICE INCLUDING OVERLAY PATTERNS
A semiconductor device includes a first overlay group and a second overlay group disposed on a semiconductor substrate. The first overlay group includes first...
2018/0175015 METHOD FOR FABRICATING DAMASCENE STRUCTURE USING FLUOROCARBON FILM
A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a dielectric layer on the metal interconnect layer,...
2018/0175014 SEMICONDUCTOR DEVICE
In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween....
2018/0175013 Wafer-Level Underfill and Over-Molding
A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring...
2018/0175012 SEAL RING STRUCTURES AND METHODS OF FORMING SAME
A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a...
2018/0175011 SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME
A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an...
2018/0175009 LIGHT EMITTING DEVICE AND DISPLAY DEVICE INCLUDING THE SAME
A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second...
2018/0175008 THREE DIMENSIONAL INTEGRATED CIRCUIT
A device is formed by providing a first substrate, depositing a thickness of range compensating material on a first surface of the first substrate, implanting...
2018/0175007 PRESSURE CONTACT-TYPE SEMICONDUCTOR MODULE
A pressure contact-type semiconductor module includes a plurality of semiconductor units disposed side-by-side, each of the semiconductor units including: a...
2018/0175006 SEMICONDUCTOR DEVICE INCLUDING DIE BOND PADS AT A DIE EDGE
A semiconductor device is disclosed that is formed with die bond pads at an edge of the semiconductor die. The die bond pads may be formed partially in a kerf...
2018/0175005 THERMAL DISSIPATION USING ANISOTROPIC CONDUCTIVE MATERIAL
Various embodiments disclosed relate to an integrated circuit package. The integrated circuit package includes a substrate. A first die is attached to the...
2018/0175004 THREE DIMENSIONAL INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THEREOF
A three dimensional integrated circuit (3DIC) package includes a redistribution layer, a plurality of semiconductor chips and a plurality of electrical...
2018/0175003 PACKAGE ON PACKAGE CONFIGURATION
A first integrated circuit (IC) package has a package substrate on bottom. The package substrate comprises a bottom redistribution circuitry configured...
2018/0175002 PACKAGE-BOTTOM INTERPOSERS FOR LAND-SIDE CONFIGURED DEVICES FOR SYSTEM-IN-PACKAGE APPARATUS
A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a package bottom interposer...
2018/0175001 SEMICONDUCTOR PACKAGE
A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second...
2018/0175000 HYBRID DIE STACKING
Disclosed is a die stack. The die stack may include a first plurality of dies and a second plurality of dies. Each of the plurality of dies may define a...
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